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来自「游戏玩家通过控制PS/2键盘上的方向键」· LOG 代码 · 共 1,781 行 · 第 1/5 页

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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/ASIC设计/zoumigong/keyboard.vhd" in Library work.
Architecture behavioral of Entity keyboard is up to date.
Compiling vhdl file "D:/ASIC设计/zoumigong/vga.vhd" in Library work.
Architecture behavioral of Entity vga is up to date.
Compiling verilog file "div_clk_25Mhz.v"
Module <div_clk_25Mhz> compiled
Compiling verilog file "div16.v"
Module <div16> compiled
Compiling verilog file "mux2_1_6bits.v"
Module <mux2_1_6bits> compiled
Compiling verilog file "rom_labirint.v"
Module <rom_labirint> compiled
Compiling verilog file "reg_6bits.v"
Module <reg_6bits> compiled
Compiling verilog file "rom_empty_char.v"
Module <rom_empty_char> compiled
Compiling verilog file "rom_human_char.v"
Module <rom_human_char> compiled
Compiling verilog file "rom_wall_char.v"
Module <rom_wall_char> compiled
Compiling verilog file "rom_door_char.v"
Module <rom_door_char> compiled
Compiling verilog file "mux8_1_3bits.v"
Module <mux8_1_3bits> compiled
Compiling verilog file "char_generator.v"
Module <char_generator> compiled
Compiling verilog file "newPositions.v"
Module <newPositions> compiled
Compiling verilog file "validate_positions.v"
Module <validate_positions> compiled
Compiling verilog file "div_clk_6hz.v"
Module <div_clk_6hz> compiled
Compiling verilog file "light.v"
Module <light> compiled
Compiling verilog file "div_clk_381hz.v"
Module <div_clk_381hz> compiled
Compiling verilog file "num_2bits.v"
Module <num_2bits> compiled
Compiling verilog file "decod_2bits.v"
Module <decod_2bits> compiled
Compiling verilog file "mux4_1_4bits.v"
Module <mux4_1_4bits> compiled
Compiling verilog file "rom_digits.v"
Module <rom_digits> compiled
Compiling verilog file "seg7_display.v"
Module <seg7_display> compiled
Compiling verilog file "timer.v"
Module <timer> compiled
Compiling verilog file "timer_enable.v"
Module <timer_enable> compiled
Compiling verilog file "top_zoumigong.v"
Module <top_zoumigong> compiled
No errors in compilation
Analysis of file <"top_zoumigong.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <top_zoumigong>.
Module <top_zoumigong> is correct for synthesis.
 
Analyzing module <div_clk_25Mhz>.
Module <div_clk_25Mhz> is correct for synthesis.
 
Analyzing Entity <vga> (Architecture <behavioral>).
Entity <vga> analyzed. Unit <vga> generated.

Analyzing module <div16>.
Module <div16> is correct for synthesis.
 
Analyzing module <mux2_1_6bits>.
Module <mux2_1_6bits> is correct for synthesis.
 
Analyzing module <rom_labirint>.
Module <rom_labirint> is correct for synthesis.
 
Analyzing module <reg_6bits>.
Module <reg_6bits> is correct for synthesis.
 
Analyzing module <char_generator>.
Module <char_generator> is correct for synthesis.
 
Analyzing module <rom_empty_char>.
Module <rom_empty_char> is correct for synthesis.
 
Analyzing module <rom_human_char>.
Module <rom_human_char> is correct for synthesis.
 
Analyzing module <rom_wall_char>.
Module <rom_wall_char> is correct for synthesis.
 
Analyzing module <rom_door_char>.
Module <rom_door_char> is correct for synthesis.
 
Analyzing module <mux8_1_3bits>.
Module <mux8_1_3bits> is correct for synthesis.
 
Analyzing Entity <keyboard> (Architecture <behavioral>).
Entity <keyboard> analyzed. Unit <keyboard> generated.

Analyzing module <newPositions>.
Module <newPositions> is correct for synthesis.
 
Analyzing module <validate_positions>.
Module <validate_positions> is correct for synthesis.
 
Analyzing module <div_clk_6hz>.
	value = 416666
Module <div_clk_6hz> is correct for synthesis.
 
Analyzing module <light>.
Module <light> is correct for synthesis.
 
Analyzing module <seg7_display>.
Module <seg7_display> is correct for synthesis.
 
Analyzing module <div_clk_381hz>.
Module <div_clk_381hz> is correct for synthesis.
 
Analyzing module <num_2bits>.
Module <num_2bits> is correct for synthesis.
 
Analyzing module <decod_2bits>.
Module <decod_2bits> is correct for synthesis.
 
Analyzing module <mux4_1_4bits>.
Module <mux4_1_4bits> is correct for synthesis.
 
Analyzing module <rom_digits>.
Module <rom_digits> is correct for synthesis.
 
Analyzing module <timer>.
	value = 24999999
Module <timer> is correct for synthesis.
 
Analyzing module <timer_enable>.
Module <timer_enable> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <dir> in unit <light> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <rom_digits>.
    Related source file is "rom_digits.v".
    Found 16x8-bit ROM for signal <digit>.
    Summary:
	inferred   1 ROM(s).
Unit <rom_digits> synthesized.


Synthesizing Unit <mux4_1_4bits>.
    Related source file is "mux4_1_4bits.v".
    Found 4-bit 4-to-1 multiplexer for signal <o>.
    Summary:
	inferred   4 Multiplexer(s).
Unit <mux4_1_4bits> synthesized.


Synthesizing Unit <decod_2bits>.
    Related source file is "decod_2bits.v".
    Found 1-bit 4-to-1 multiplexer for signal <o0>.
    Found 1-bit 4-to-1 multiplexer for signal <o1>.
    Found 1-bit 4-to-1 multiplexer for signal <o2>.
    Found 1-bit 4-to-1 multiplexer for signal <o3>.
    Summary:
	inferred   4 Multiplexer(s).
Unit <decod_2bits> synthesized.


Synthesizing Unit <num_2bits>.
    Related source file is "num_2bits.v".
    Found 2-bit register for signal <val>.
    Found 2-bit up counter for signal <val1>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <num_2bits> synthesized.


Synthesizing Unit <div_clk_381hz>.
    Related source file is "div_clk_381hz.v".
    Found 17-bit up counter for signal <clk>.
    Summary:
	inferred   1 Counter(s).
Unit <div_clk_381hz> synthesized.


Synthesizing Unit <mux8_1_3bits>.
    Related source file is "mux8_1_3bits.v".
    Found 3-bit 8-to-1 multiplexer for signal <o>.
    Summary:
	inferred   3 Multiplexer(s).
Unit <mux8_1_3bits> synthesized.


Synthesizing Unit <rom_door_char>.
    Related source file is "rom_door_char.v".
    Found 16x48-bit ROM for signal <rom_line>.
    Found 3-bit 16-to-1 multiplexer for signal <color>.
    Summary:
	inferred   1 ROM(s).
	inferred   3 Multiplexer(s).
Unit <rom_door_char> synthesized.


Synthesizing Unit <rom_wall_char>.
    Related source file is "rom_wall_char.v".
    Found 16x48-bit ROM for signal <rom_line>.
    Found 3-bit 16-to-1 multiplexer for signal <color>.
    Summary:
	inferred   1 ROM(s).
	inferred   3 Multiplexer(s).
Unit <rom_wall_char> synthesized.


Synthesizing Unit <rom_human_char>.
    Related source file is "rom_human_char.v".
    Found 16x48-bit ROM for signal <rom_line>.
    Found 3-bit 16-to-1 multiplexer for signal <color>.
    Summary:
	inferred   1 ROM(s).
	inferred   3 Multiplexer(s).
Unit <rom_human_char> synthesized.


Synthesizing Unit <rom_empty_char>.
    Related source file is "rom_empty_char.v".
Unit <rom_empty_char> synthesized.


Synthesizing Unit <timer_enable>.
    Related source file is "timer_enable.v".
WARNING:Xst:737 - Found 1-bit latch for signal <enable>.
Unit <timer_enable> synthesized.


Synthesizing Unit <timer>.
    Related source file is "timer.v".
    Found 4-bit up counter for signal <d1>.
    Found 4-bit up counter for signal <d2>.
    Found 4-bit up counter for signal <d3>.
    Found 4-bit up counter for signal <d4>.
    Found 1-bit register for signal <clk_1hz>.
    Found 32-bit up counter for signal <i>.
    Summary:
	inferred   5 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <timer> synthesized.


Synthesizing Unit <seg7_display>.
    Related source file is "seg7_display.v".
Unit <seg7_display> synthesized.


Synthesizing Unit <light>.
    Related source file is "light.v".
    Found finite state machine <FSM_0> for signal <led>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 10                                             |
    | Inputs             | 0                                              |
    | Outputs            | 9                                              |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | done (positive)                                |
    | Reset              | reset (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 00000000                                       |
    | Power Up State     | 00000000                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 Finite State Machine(s).
Unit <light> synthesized.


Synthesizing Unit <div_clk_6hz>.
    Related source file is "div_clk_6hz.v".
    Found 1-bit register for signal <clk23b>.
    Found 32-bit up counter for signal <i>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <div_clk_6hz> synthesized.


Synthesizing Unit <validate_positions>.
    Related source file is "validate_positions.v".
    Found 1-bit register for signal <S>.
    Found 1-bit register for signal <done>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <validate_positions> synthesized.


Synthesizing Unit <newPositions>.
    Related source file is "newPositions.v".
    Found 6-bit register for signal <NC>.
    Found 6-bit register for signal <NR>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0002> created at line 38.
    Found 6-bit addsub for signal <$n0007>.
    Found 6-bit addsub for signal <$n0008>.
    Found 1-bit register for signal <o>.
    Summary:
	inferred  13 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Multiplexer(s).
Unit <newPositions> synthesized.


Synthesizing Unit <keyboard>.
    Related source file is "D:/ASIC设计/zoumigong/keyboard.vhd".
    Found 1-bit register for signal <RDY>.
    Found 4-bit up counter for signal <clkDiv>.
    Found 1-bit register for signal <DFF1>.
    Found 1-bit register for signal <DFF2>.
    Found 1-bit register for signal <KCI>.
    Found 1-bit register for signal <KDI>.
    Found 8-bit register for signal <lastvalue>.
    Found 1-bit register for signal <receivedChar>.
    Found 3-bit shift register for signal <shiftRegSig1<8>>.
    Found 7-bit register for signal <shiftRegSig1<7:1>>.
    Found 4-bit shift register for signal <shiftRegSig2<8>>.
    Found 7-bit register for signal <shiftRegSig2<7:1>>.
    Found 8-bit register for signal <WaitReg>.
    Summary:
	inferred   1 Counter(s).
	inferred  36 D-type flip-flop(s).
	inferred   2 Shift register(s).
Unit <keyboard> synthesized.


Synthesizing Unit <char_generator>.
    Related source file is "char_generator.v".
    Found 6-bit comparator equa