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=========================================================================

Optimizing unit <div_clk_6hz> ...
Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block div_clk_6hz, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                      12  out of   3584     0%  
 Number of Slice Flip Flops:            23  out of   7168     0%  
 Number of 4 input LUTs:                22  out of   7168     0%  
 Number of bonded IOBs:                  2  out of    141     1%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clock_50Mhz                        | BUFGP                  | 23    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 4.588ns (Maximum Frequency: 217.967MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 6.280ns
   Maximum combinational path delay: No path found

=========================================================================


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "div_clk_6hz.v"
Module <div_clk_6hz> compiled
No errors in compilation
Analysis of file <"div_clk_6hz.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <div_clk_6hz>.
	value = 416666
Module <div_clk_6hz> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <div_clk_6hz>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <div_clk_6hz>.
    Related source file is "div_clk_6hz.v".
    Found 1-bit register for signal <clk23b>.
    Found 32-bit up counter for signal <i>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <div_clk_6hz> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 32-bit up counter                 : 1
# Registers                        : 1
 1-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <div_clk_6hz> ...
Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block div_clk_6hz, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                      30  out of   3584     0%  
 Number of Slice Flip Flops:            33  out of   7168     0%  
 Number of 4 input LUTs:                46  out of   7168     0%  
 Number of bonded IOBs:                  2  out of    141     1%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clock_50Mhz                        | BUFGP                  | 33    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 6.698ns (Maximum Frequency: 149.305MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 6.280ns
   Maximum combinational path delay: No path found

=========================================================================


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/ASIC设计/zoumigong/keyboard.vhd" in Library work.
Architecture behavioral of Entity keyboard is up to date.
Compiling vhdl file "D:/ASIC设计/zoumigong/vga.vhd" in Library work.
Architecture behavioral of Entity vga is up to date.
Compiling verilog file "div_clk_25Mhz.v"
Module <div_clk_25Mhz> compiled
Compiling verilog file "div16.v"
Module <div16> compiled
Compiling verilog file "mux2_1_6bits.v"
Module <mux2_1_6bits> compiled
Compiling verilog file "rom_labirint.v"
Module <rom_labirint> compiled
Compiling verilog file "reg_6bits.v"
Module <reg_6bits> compiled
Compiling verilog file "rom_empty_char.v"
Module <rom_empty_char> compiled
Compiling verilog file "rom_human_char.v"
Module <rom_human_char> compiled
Compiling verilog file "rom_wall_char.v"
Module <rom_wall_char> compiled
Compiling verilog file "rom_door_char.v"
Module <rom_door_char> compiled
Compiling verilog file "mux8_1_3bits.v"
Module <mux8_1_3bits> compiled
Compiling verilog file "char_generator.v"
Module <char_generator> compiled
Compiling verilog file "newPositions.v"
Module <newPositions> compiled
Compiling verilog file "validate_positions.v"
Module <validate_positions> compiled
Compiling verilog file "div_clk_6hz.v"
Module <div_clk_6hz> compiled
Compiling verilog file "light.v"
Module <light> compiled
Compiling verilog file "div_clk_381hz.v"
Module <div_clk_381hz> compiled
Compiling verilog file "num_2bits.v"
Module <num_2bits> compiled
Compiling verilog file "decod_2bits.v"
Module <decod_2bits> compiled
Compiling verilog file "mux4_1_4bits.v"
Module <mux4_1_4bits> compiled
Compiling verilog file "rom_digits.v"
Module <rom_digits> compiled
Compiling verilog file "seg7_display.v"
Module <seg7_display> compiled
Compiling verilog file "timer.v"
Module <timer> compiled
Compiling verilog file "timer_enable.v"
Module <timer_enable> compiled
Compiling verilog file "top_zoumigong.v"
Module <top_zoumigong> compiled
No errors in compilation
Analysis of file <"top_zoumigong.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <top_zoumigong>.
Module <top_zoumigong> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <top_zoumigong>.
Analyzing module <div_clk_25Mhz>.
Module <div_clk_25Mhz> is correct for synthesis.
 
Analyzing Entity <vga> (Architecture <behavioral>).
Entity <vga> analyzed. Unit <vga> generated.

Analyzing module <div16>.
Module <div16> is correct for synthesis.
 
Analyzing module <mux2_1_6bits>.
Module <mux2_1_6bits> is correct for synthesis.
 
Analyzing module <rom_labirint>.
Module <rom_labirint> is correct for synthesis.
 
Analyzing module <reg_6bits>.
Module <reg_6bits> is correct for synthesis.
 
Analyzing module <char_generator>.
Module <char_generator> is correct for synthesis.
 
Analyzing module <rom_empty_char>.
Module <rom_empty_char> is correct for synthesis.
 
Analyzing module <rom_human_char>.
Module <rom_human_char> is correct for synthesis.
 
Analyzing module <rom_wall_char>.
Module <rom_wall_char> is correct for synthesis.
 
Analyzing module <rom_door_char>.
Module <rom_door_char> is correct for synthesis.
 
Analyzing module <mux8_1_3bits>.
Module <mux8_1_3bits> is correct for synthesis.
 
Analyzing Entity <keyboard> (Architecture <behavioral>).
Entity <keyboard> analyzed. Unit <keyboard> generated.

Analyzing module <newPositions>.
Module <newPositions> is correct for synthesis.
 
Analyzing module <validate_positions>.
Module <validate_positions> is correct for synthesis.
 
Analyzing module <div_clk_6hz>.
	value = 416666
Module <div_clk_6hz> is correct for synthesis.
 
Analyzing module <light>.
Module <light> is correct for synthesis.
 
Analyzing module <seg7_display>.
Module <seg7_display> is correct for synthesis.
 
Analyzing module <div_clk_381hz>.
Module <div_clk_381hz> is correct for synthesis.
 
Analyzing module <num_2bits>.
Module <num_2bits> is correct for synthesis.
 
Analyzing module <decod_2bits>.
Module <decod_2bits> is correct for synthesis.
 
Analyzing module <mux4_1_4bits>.
Module <mux4_1_4bits> is correct for synthesis.
 
Analyzing module <rom_digits>.
Module <rom_digits> is correct for synthesis.
 
Analyzing module <timer>.
	value = 24999999
Module <timer> is correct for synthesis.
 
Analyzing module <timer_enable>.
Module <timer_enable> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <dir> in unit <light> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <rom_digits>.
    Related source file is "rom_digits.v".
    Found 16x8-bit ROM for signal <digit>.
    Summary:
	inferred   1 ROM(s).
Unit <rom_digits> synthesized.


Synthesizing Unit <mux4_1_4bits>.
    Related source file is "mux4_1_4bits.v".
    Found 4-bit 4-to-1 multiplexer for signal <o>.
    Summary:
	inferred   4 Multiplexer(s).
Unit <mux4_1_4bits> synthesized.


Synthesizing Unit <decod_2bits>.
    Related source file is "decod_2bits.v".
    Found 1-bit 4-to-1 multiplexer for signal <o0>.
    Found 1-bit 4-to-1 multiplexer for signal <o1>.
    Found 1-bit 4-to-1 multiplexer for signal <o2>.
    Found 1-bit 4-to-1 multiplexer for signal <o3>.
    Summary:
	inferred   4 Multiplexer(s).
Unit <decod_2bits> synthesized.