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--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    10:19:33 04/30/09
-- Design Name:    
-- Module Name:    vga - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity VGA is
	port( clock_25Mhz, red, green, blue : in std_logic;
			red_out, green_out, blue_out : out std_logic;
			horiz_sync_out, vert_sync_out : out std_logic;
			pixel_row, pixel_column : out std_logic_vector(9 downto 0));
end VGA;

architecture Behavioral of VGA is

signal horiz_sync, vert_sync : std_logic;
signal video_on, video_on_v, video_on_h : std_logic;
signal h_count, v_count : std_logic_vector(9 downto 0);

begin


	video_on <= video_on_H and video_on_V;

	process
	begin
		wait until(clock_25Mhz'EVENT) and (clock_25Mhz='1');

		if (h_count = 799) then
			h_count <= "0000000000";
		else
			h_count <= h_count + 1;
		end if;

		if (h_count <= 755) and (h_count >= 659) then
			horiz_sync <= '0';
		else
			horiz_sync <= '1';
		end if;
	
		if (v_count >= 524) and (h_count >= 699) then
			v_count <= "0000000000";
		elsif (h_count = 699) then
			v_count <= v_count + 1;
		end if;
		
		if (v_count <= 494) and (v_count >= 493) then
			vert_sync <= '0';
		else
			vert_sync <= '1';
		end if;

		if (h_count <= 639) then
			video_on_h <= '1';
			pixel_column <= h_count;
		else
			video_on_h <= '0';
		end if;
		if (v_count <= 479) then
			video_on_v <= '1';
			pixel_row <= v_count;
		else
			video_on_v <= '0';
		end if;

		red_out <= red and video_on;
		green_out <= green and video_on;
		blue_out <= blue and video_on;
		horiz_sync_out <= horiz_sync;
		vert_sync_out <= vert_sync;
	end process;
end Behavioral;

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