timer.syr

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Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: timer.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "timer.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "timer"
Output Format                      : NGC
Target Device                      : xc3s400-5-pq208

---- Source Options
Top Module Name                    : timer
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : timer.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "timer.v"
Module <timer> compiled
No errors in compilation
Analysis of file <"timer.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <timer>.
	value = 24999999
Module <timer> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <timer>.
    Related source file is "timer.v".
    Found 4-bit up counter for signal <d1>.
    Found 4-bit up counter for signal <d2>.
    Found 4-bit up counter for signal <d3>.
    Found 4-bit up counter for signal <d4>.
    Found 1-bit register for signal <clk_1hz>.
    Found 32-bit up counter for signal <i>.
    Summary:
	inferred   5 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <timer> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 5
 32-bit up counter                 : 1
 4-bit up counter                  : 4
# Registers                        : 1
 1-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <timer> ...
Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block timer, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : timer.ngr
Top Level Output File Name         : timer
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 19

Macro Statistics :
# Registers                        : 6
#      1-bit register              : 1
#      4-bit register              : 5

Cell Usage :
# BELS                             : 142
#      GND                         : 1
#      INV                         : 6
#      LUT1                        : 9
#      LUT1_L                      : 22
#      LUT2                        : 7
#      LUT2_L                      : 2
#      LUT3                        : 7
#      LUT3_L                      : 1
#      LUT4                        : 19
#      LUT4_D                      : 3
#      LUT4_L                      : 2
#      MUXCY                       : 31
#      VCC                         : 1
#      XORCY                       : 31
# FlipFlops/Latches                : 49
#      FDE                         : 1
#      FDR                         : 32
#      FDRE                        : 16
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 18
#      IBUF                        : 2
#      OBUF                        : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                      47  out of   3584     1%  
 Number of Slice Flip Flops:            49  out of   7168     0%  
 Number of 4 input LUTs:                72  out of   7168     1%  
 Number of bonded IOBs:                 19  out of    141    13%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 33    |
clk_1hz:Q                          | NONE                   | 16    |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 6.573ns (Maximum Frequency: 152.144MHz)
   Minimum input arrival time before clock: 6.732ns
   Maximum output required time after clock: 6.441ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 6.573ns (frequency: 152.144MHz)
  Total number of paths / destination ports: 1585 / 66
-------------------------------------------------------------------------
Delay:               6.573ns (Levels of Logic = 3)
  Source:            i_11 (FF)
  Destination:       i_30 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: i_11 to i_30
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.626   1.040  i_11 (i_11)
     LUT4:I0->O            1   0.479   0.704  _n000041 (CHOICE168)
     LUT4:I3->O            5   0.479   0.953  _n000044 (CHOICE169)
     LUT4:I1->O            8   0.479   0.921  _n0000141_1 (_n0000141)
     FDR:R                     0.892          i_0
    ----------------------------------------
    Total                      6.573ns (2.955ns logic, 3.618ns route)
                                       (45.0% logic, 55.0% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk_1hz:Q'
  Clock period: 6.450ns (frequency: 155.046MHz)
  Total number of paths / destination ports: 296 / 44
-------------------------------------------------------------------------
Delay:               6.450ns (Levels of Logic = 3)
  Source:            d2_1 (FF)
  Destination:       d2_3 (FF)
  Source Clock:      clk_1hz:Q rising
  Destination Clock: clk_1hz:Q rising

  Data Path: d2_1 to d2_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             6   0.626   1.023  d2_1 (d2_1)
     LUT3:I1->O            1   0.479   0.740  Ker0_SW0_SW0 (N111)
     LUT4:I2->O            5   0.479   0.953  Ker0 (N01)
     LUT2:I1->O            4   0.479   0.779  _n00061 (_n0006)
     FDRE:R                    0.892          d2_0
    ----------------------------------------
    Total                      6.450ns (2.955ns logic, 3.495ns route)
                                       (45.8% logic, 54.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_1hz:Q'
  Total number of paths / destination ports: 48 / 32
-------------------------------------------------------------------------
Offset:              6.732ns (Levels of Logic = 4)
  Source:            enable (PAD)
  Destination:       d2_3 (FF)
  Destination Clock: clk_1hz:Q rising

  Data Path: enable to d2_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             8   0.715   1.216  enable_IBUF (enable_IBUF)
     LUT3:I0->O            1   0.479   0.740  Ker0_SW0_SW0 (N111)
     LUT4:I2->O            5   0.479   0.953  Ker0 (N01)
     LUT2:I1->O            4   0.479   0.779  _n00061 (_n0006)
     FDRE:R                    0.892          d2_0
    ----------------------------------------
    Total                      6.732ns (3.044ns logic, 3.688ns route)
                                       (45.2% logic, 54.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_1hz:Q'
  Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Offset:              6.441ns (Levels of Logic = 1)
  Source:            d1_0 (FF)
  Destination:       d1<0> (PAD)
  Source Clock:      clk_1hz:Q rising

  Data Path: d1_0 to d1<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             7   0.626   0.906  d1_0 (d1_0)
     OBUF:I->O                 4.909          d1_0_OBUF (d1<0>)
    ----------------------------------------
    Total                      6.441ns (5.535ns logic, 0.906ns route)
                                       (85.9% logic, 14.1% route)

=========================================================================
CPU : 6.41 / 6.84 s | Elapsed : 6.00 / 6.00 s
 
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Total memory usage is 102080 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)