newpositions.syr

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Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: newPositions.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "newPositions.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "newPositions"
Output Format                      : NGC
Target Device                      : xc3s400-5-pq208

---- Source Options
Top Module Name                    : newPositions
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : newPositions.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "newPositions.v"
Module <newPositions> compiled
No errors in compilation
Analysis of file <"newPositions.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <newPositions>.
Module <newPositions> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <newPositions>.
    Related source file is "newPositions.v".
    Found 6-bit register for signal <NC>.
    Found 6-bit register for signal <NR>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0002> created at line 38.
    Found 6-bit addsub for signal <$n0007>.
    Found 6-bit addsub for signal <$n0008>.
    Found 1-bit register for signal <o>.
    Summary:
	inferred  13 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Multiplexer(s).
Unit <newPositions> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 2
 6-bit addsub                      : 2
# Registers                        : 3
 1-bit register                    : 1
 6-bit register                    : 2
# Multiplexers                     : 1
 1-bit 4-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <newPositions> ...
Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block newPositions, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : newPositions.ngr
Top Level Output File Name         : newPositions
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 35

Macro Statistics :
# Registers                        : 3
#      1-bit register              : 1
#      6-bit register              : 2
# Multiplexers                     : 1
#      1-bit 4-to-1 multiplexer    : 1
# Adders/Subtractors               : 2
#      6-bit addsub                : 2

Cell Usage :
# BELS                             : 73
#      LUT2                        : 12
#      LUT3                        : 5
#      LUT4                        : 20
#      LUT4_L                      : 12
#      MUXCY                       : 10
#      MUXF5                       : 2
#      XORCY                       : 12
# FlipFlops/Latches                : 13
#      FDE                         : 13
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 34
#      IBUF                        : 21
#      OBUF                        : 13
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                      27  out of   3584     0%  
 Number of Slice Flip Flops:            13  out of   7168     0%  
 Number of 4 input LUTs:                49  out of   7168     0%  
 Number of bonded IOBs:                 35  out of    141    24%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 13    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 2.049ns (Maximum Frequency: 487.936MHz)
   Minimum input arrival time before clock: 10.127ns
   Maximum output required time after clock: 6.280ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 2.049ns (frequency: 487.936MHz)
  Total number of paths / destination ports: 12 / 12
-------------------------------------------------------------------------
Delay:               2.049ns (Levels of Logic = 1)
  Source:            NR_4 (FF)
  Destination:       NR_4 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: NR_4 to NR_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.626   0.768  NR_4 (NR_4)
     LUT4_L:I3->LO         1   0.479   0.000  _n0000<4> (_n0000<4>)
     FDE:D                     0.176          NR_4
    ----------------------------------------
    Total                      2.049ns (1.281ns logic, 0.768ns route)
                                       (62.5% logic, 37.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 889 / 26
-------------------------------------------------------------------------
Offset:              10.127ns (Levels of Logic = 12)
  Source:            key<7> (PAD)
  Destination:       NR_5 (FF)
  Destination Clock: clk rising

  Data Path: key<7> to NR_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             3   0.715   1.066  key_7_IBUF (key_7_IBUF)
     LUT3:I0->O           14   0.479   1.304  Ker171 (N17)
     LUT4:I0->O            7   0.479   1.076  _n0011 (_n0011)
     LUT2:I1->O            1   0.479   0.000  newPositions__n0007<0>lut (N4)
     MUXCY:S->O            1   0.435   0.000  newPositions__n0007<0>cy (newPositions__n0007<0>_cyo)
     MUXCY:CI->O           1   0.056   0.000  newPositions__n0007<1>cy (newPositions__n0007<1>_cyo)
     MUXCY:CI->O           1   0.055   0.000  newPositions__n0007<2>cy (newPositions__n0007<2>_cyo)
     MUXCY:CI->O           1   0.056   0.000  newPositions__n0007<3>cy (newPositions__n0007<3>_cyo)
     MUXCY:CI->O           0   0.056   0.000  newPositions__n0007<4>cy (newPositions__n0007<4>_cyo)
     XORCY:CI->O           1   0.786   0.976  newPositions__n0007<5>_xor (_n0007<5>)
     LUT4:I0->O            1   0.479   0.976  _n0000<5>_SW0 (N39)
     LUT4_L:I0->LO         1   0.479   0.000  _n0000<5> (_n0000<5>)
     FDE:D                     0.176          NR_5
    ----------------------------------------
    Total                     10.127ns (4.729ns logic, 5.398ns route)
                                       (46.7% logic, 53.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 13 / 13
-------------------------------------------------------------------------
Offset:              6.280ns (Levels of Logic = 1)
  Source:            NC_5 (FF)
  Destination:       NC<5> (PAD)
  Source Clock:      clk rising

  Data Path: NC_5 to NC<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.626   0.745  NC_5 (NC_5)
     OBUF:I->O                 4.909          NC_5_OBUF (NC<5>)
    ----------------------------------------
    Total                      6.280ns (5.535ns logic, 0.745ns route)
                                       (88.1% logic, 11.9% route)

=========================================================================
CPU : 5.83 / 6.23 s | Elapsed : 6.00 / 6.00 s
 
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Total memory usage is 102080 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)