seg7_display.syr

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*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <seg7_display> ...
Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block seg7_display, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : seg7_display.ngr
Top Level Output File Name         : seg7_display
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 29

Macro Statistics :
# ROMs                             : 1
#      16x8-bit ROM                : 1
# Registers                        : 3
#      17-bit register             : 2
#      2-bit register              : 1
# Multiplexers                     : 5
#      1-bit 4-to-1 multiplexer    : 4
#      4-bit 4-to-1 multiplexer    : 1
# Adders/Subtractors               : 2
#      17-bit adder                : 2

Cell Usage :
# BELS                             : 75
#      GND                         : 1
#      INV                         : 1
#      LUT1_L                      : 16
#      LUT2                        : 5
#      LUT3                        : 8
#      LUT4                        : 7
#      MUXCY                       : 16
#      MUXF5                       : 4
#      VCC                         : 1
#      XORCY                       : 16
# FlipFlops/Latches                : 21
#      FD                          : 20
#      FDR                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 28
#      IBUF                        : 16
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                      20  out of   3584     0%  
 Number of Slice Flip Flops:            21  out of   7168     0%  
 Number of 4 input LUTs:                36  out of   7168     0%  
 Number of bonded IOBs:                 29  out of    141    20%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 17    |
divclk/clk_16:Q                    | NONE                   | 4     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 4.255ns (Maximum Frequency: 235.026MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 9.934ns
   Maximum combinational path delay: 9.629ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 4.255ns (frequency: 235.026MHz)
  Total number of paths / destination ports: 153 / 17
-------------------------------------------------------------------------
Delay:               4.255ns (Levels of Logic = 17)
  Source:            divclk/clk_1 (FF)
  Destination:       divclk/clk_16 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: divclk/clk_1 to divclk/clk_16
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.626   0.976  divclk/clk_1 (divclk/clk_1)
     LUT1_L:I0->LO         1   0.479   0.000  divclk/clk_1_rt (divclk/clk_1_rt)
     MUXCY:S->O            1   0.435   0.000  seg7_display_divclk/clk__n0000<1>cy (seg7_display_divclk/clk__n0000<1>_cyo)
     MUXCY:CI->O           1   0.056   0.000  seg7_display_divclk/clk__n0000<2>cy (seg7_display_divclk/clk__n0000<2>_cyo)
     MUXCY:CI->O           1   0.056   0.000  seg7_display_divclk/clk__n0000<3>cy (seg7_display_divclk/clk__n0000<3>_cyo)
     MUXCY:CI->O           1   0.056   0.000  seg7_display_divclk/clk__n0000<4>cy (seg7_display_divclk/clk__n0000<4>_cyo)
     MUXCY:CI->O           1   0.056   0.000  seg7_display_divclk/clk__n0000<5>cy (seg7_display_divclk/clk__n0000<5>_cyo)
     MUXCY:CI->O           1   0.056   0.000  seg7_display_divclk/clk__n0000<6>cy (seg7_display_divclk/clk__n0000<6>_cyo)
     MUXCY:CI->O           1   0.056   0.000  seg7_display_divclk/clk__n0000<7>cy (seg7_display_divclk/clk__n0000<7>_cyo)
     MUXCY:CI->O           1   0.056   0.000  seg7_display_divclk/clk__n0000<8>cy (seg7_display_divclk/clk__n0000<8>_cyo)
     MUXCY:CI->O           1   0.056   0.000  seg7_display_divclk/clk__n0000<9>cy (seg7_display_divclk/clk__n0000<9>_cyo)
     MUXCY:CI->O           1   0.056   0.000  seg7_display_divclk/clk__n0000<10>cy (seg7_display_divclk/clk__n0000<10>_cyo)
     MUXCY:CI->O           1   0.056   0.000  seg7_display_divclk/clk__n0000<11>cy (seg7_display_divclk/clk__n0000<11>_cyo)
     MUXCY:CI->O           1   0.056   0.000  seg7_display_divclk/clk__n0000<12>cy (seg7_display_divclk/clk__n0000<12>_cyo)
     MUXCY:CI->O           1   0.056   0.000  seg7_display_divclk/clk__n0000<13>cy (seg7_display_divclk/clk__n0000<13>_cyo)
     MUXCY:CI->O           1   0.056   0.000  seg7_display_divclk/clk__n0000<14>cy (seg7_display_divclk/clk__n0000<14>_cyo)
     MUXCY:CI->O           0   0.056   0.000  seg7_display_divclk/clk__n0000<15>cy (seg7_display_divclk/clk__n0000<15>_cyo)
     XORCY:CI->O           1   0.786   0.000  seg7_display_divclk/clk__n0000<16>_xor (divclk/clk__n0000<16>)
     FD:D                      0.176          divclk/clk_16
    ----------------------------------------
    Total                      4.255ns (3.279ns logic, 0.976ns route)
                                       (77.1% logic, 22.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'divclk/clk_16:Q'
  Clock period: 2.347ns (frequency: 426.085MHz)
  Total number of paths / destination ports: 5 / 4
-------------------------------------------------------------------------
Delay:               2.347ns (Levels of Logic = 1)
  Source:            num/val1_0 (FF)
  Destination:       num/val1_1 (FF)
  Source Clock:      divclk/clk_16:Q rising
  Destination Clock: divclk/clk_16:Q rising

  Data Path: num/val1_0 to num/val1_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   0.626   1.066  num/val1_0 (num/val1_0)
     LUT2:I0->O            1   0.479   0.000  num/val1_Madd__n0000_Mxor_Result<1>_Result1 (num/val1__n0000<1>)
     FD:D                      0.176          num/val1_1
    ----------------------------------------
    Total                      2.347ns (1.281ns logic, 1.066ns route)
                                       (54.6% logic, 45.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'divclk/clk_16:Q'
  Total number of paths / destination ports: 92 / 11
-------------------------------------------------------------------------
Offset:              9.934ns (Levels of Logic = 4)
  Source:            num/val_1 (FF)
  Destination:       ca (PAD)
  Source Clock:      divclk/clk_16:Q rising

  Data Path: num/val_1 to ca
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              12   0.626   1.245  num/val_1 (num/val_1)
     LUT3:I0->O            1   0.479   0.000  an1_an1111_G (N29)
     MUXF5:I1->O           7   0.314   1.201  an1_an1111 (mux_out<0>)
     LUT4:I0->O            1   0.479   0.681  rom/Mrom_digit_inst_lut4_71 (ca_OBUF)
     OBUF:I->O                 4.909          ca_OBUF (ca)
    ----------------------------------------
    Total                      9.934ns (6.807ns logic, 3.127ns route)
                                       (68.5% logic, 31.5% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 112 / 7
-------------------------------------------------------------------------
Delay:               9.629ns (Levels of Logic = 5)
  Source:            d1<0> (PAD)
  Destination:       ca (PAD)

  Data Path: d1<0> to ca
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.715   0.851  d1_0_IBUF (d1_0_IBUF)
     LUT3:I1->O            1   0.479   0.000  an1_an1111_F (N28)
     MUXF5:I0->O           7   0.314   1.201  an1_an1111 (mux_out<0>)
     LUT4:I0->O            1   0.479   0.681  rom/Mrom_digit_inst_lut4_71 (ca_OBUF)
     OBUF:I->O                 4.909          ca_OBUF (ca)
    ----------------------------------------
    Total                      9.629ns (6.896ns logic, 2.733ns route)
                                       (71.6% logic, 28.4% route)

=========================================================================
CPU : 5.13 / 5.51 s | Elapsed : 5.00 / 5.00 s
 
--> 

Total memory usage is 102080 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)