top_zoumigong.par

游戏玩家通过控制PS/2键盘上的方向键

Release 7.1i par H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

3C54931B31614C4::  Wed May 13 08:57:21 2009

par -w -intstyle ise -ol std -t 1 top_zoumigong_map.ncd top_zoumigong.ncd
top_zoumigong.pcf 


Constraints file: top_zoumigong.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment
C:/Xilinx.
   "top_zoumigong" is an NCD, version 3.1, device xc3s400, package pq208, speed
-5

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "ADVANCED 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  4 out of 8      50%
   Number of External IOBs            30 out of 141    21%
      Number of LOCed IOBs            30 out of 30    100%

   Number of Slices                  643 out of 3584   17%
      Number of SLICEMs               12 out of 1792    1%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98b5ee) REAL time: 2 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.8
......................
Phase 4.8 (Checksum:a08d17) REAL time: 2 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 2 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 3 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs 

Writing design to file top_zoumigong.ncd


Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 

Starting Router

Phase 1: 3874 unrouted;       REAL time: 3 secs 

Phase 2: 3576 unrouted;       REAL time: 3 secs 

Phase 3: 1638 unrouted;       REAL time: 4 secs 

Phase 4: 0 unrouted;       REAL time: 5 secs 


WARNING:CLK Net:display/divclk/clk<16>
may have excessive skew because 3 CLK pins and 1 NON_CLK pins
failed to route using a CLK template.

WARNING:CLK Net:ps2/clkDiv<3>
may have excessive skew because 2 CLK pins and 1 NON_CLK pins
failed to route using a CLK template.

WARNING:CLK Net:div23p/clk23b
may have excessive skew because 5 CLK pins and 1 NON_CLK pins
failed to route using a CLK template.

WARNING:CLK Net:validate_position/done
may have excessive skew because 1 CLK pins and 6 NON_CLK pins
failed to route using a CLK template.

WARNING:CLK Net:t/clk_1hz
may have excessive skew because 8 CLK pins and 1 NON_CLK pins
failed to route using a CLK template.

WARNING:CLK Net:ps2/RDY
may have excessive skew because 92 NON-CLK pins
failed to route using a CLK template.

WARNING:CLK Net:divClk_50/clk
may have excessive skew because 1 NON-CLK pins
failed to route using a CLK template.

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 4 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|   clock_50Mhz_BUFGP |      BUFGMUX1| No   |  147 |  0.019     |  0.902      |
+---------------------+--------------+------+------+------------+-------------+
|       divClk_50/clk |      BUFGMUX4| No   |   95 |  0.052     |  0.936      |
+---------------------+--------------+------+------+------------+-------------+
|             ps2/RDY |      BUFGMUX5| No   |   93 |  0.000     |  0.884      |
+---------------------+--------------+------+------+------------+-------------+
|             ps2/KCI |      BUFGMUX7| No   |   15 |  0.000     |  0.901      |
+---------------------+--------------+------+------+------------+-------------+
|display/divclk/clk<1 |              |      |      |            |             |
|                  6> |         Local|      |    4 |  0.316     |  1.573      |
+---------------------+--------------+------+------+------------+-------------+
|       ps2/clkDiv<3> |         Local|      |    5 |  0.525     |  1.889      |
+---------------------+--------------+------+------+------------+-------------+
|validate_position/do |              |      |      |            |             |
|                  ne |         Local|      |    7 |  0.000     |  0.940      |
+---------------------+--------------+------+------+------------+-------------+
|       div23p/clk23b |         Local|      |    6 |  1.191     |  2.232      |
+---------------------+--------------+------+------+------------+-------------+
|           t/clk_1hz |         Local|      |    9 |  0.609     |  1.285      |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 - 
   The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  88 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file top_zoumigong.ncd



PAR done!