keyboard.syr

游戏玩家通过控制PS/2键盘上的方向键

#      3-bit shift register        : 1
#      4-bit shift register        : 1

Cell Usage :
# BELS                             : 9
#      GND                         : 1
#      INV                         : 1
#      LUT2                        : 1
#      LUT2_L                      : 1
#      LUT3                        : 1
#      LUT4                        : 3
#      VCC                         : 1
# FlipFlops/Latches                : 43
#      FD                          : 7
#      FD_1                        : 14
#      FDCE                        : 9
#      FDE                         : 8
#      FDE_1                       : 2
#      FDR                         : 3
# Shifters                         : 2
#      SRL16E_1                    : 2
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 11
#      IBUF                        : 2
#      OBUF                        : 9
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                      26  out of   3584     0%  
 Number of Slice Flip Flops:            43  out of   7168     0%  
 Number of 4 input LUTs:                 8  out of   7168     0%  
 Number of bonded IOBs:                 12  out of    141     8%  
 Number of GCLKs:                        2  out of      8    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 14    |
KCI:Q                              | BUFG                   | 27    |
clkDiv_3:Q                         | NONE                   | 4     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 9.558ns (Maximum Frequency: 104.622MHz)
   Minimum input arrival time before clock: 1.572ns
   Maximum output required time after clock: 6.216ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'KCI:Q'
  Clock period: 9.558ns (frequency: 104.622MHz)
  Total number of paths / destination ports: 97 / 34
-------------------------------------------------------------------------
Delay:               4.779ns (Levels of Logic = 2)
  Source:            shiftRegSig2_1 (FF)
  Destination:       WaitReg_7 (FF)
  Source Clock:      KCI:Q falling
  Destination Clock: KCI:Q rising

  Data Path: shiftRegSig2_1 to WaitReg_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD_1:C->Q             1   0.626   0.976  shiftRegSig2_1 (shiftRegSig2_1)
     LUT4:I0->O            1   0.479   0.740  _n000117 (CHOICE31)
     LUT4:I2->O            9   0.479   0.955  _n000120 (_n0001)
     FDCE:CE                   0.524          WaitReg_1
    ----------------------------------------
    Total                      4.779ns (2.108ns logic, 2.671ns route)
                                       (44.1% logic, 55.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clkDiv_3:Q'
  Clock period: 1.483ns (frequency: 674.377MHz)
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay:               1.483ns (Levels of Logic = 0)
  Source:            DFF1 (FF)
  Destination:       KDI (FF)
  Source Clock:      clkDiv_3:Q rising
  Destination Clock: clkDiv_3:Q rising

  Data Path: DFF1 to KDI
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.626   0.681  DFF1 (DFF1)
     FD:D                      0.176          KDI
    ----------------------------------------
    Total                      1.483ns (0.802ns logic, 0.681ns route)
                                       (54.1% logic, 45.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 2.359ns (frequency: 423.935MHz)
  Total number of paths / destination ports: 10 / 4
-------------------------------------------------------------------------
Delay:               2.359ns (Levels of Logic = 1)
  Source:            clkDiv_3 (FF)
  Destination:       clkDiv_3 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: clkDiv_3 to clkDiv_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               5   0.626   1.078  clkDiv_3 (clkDiv_3)
     LUT4:I0->O            1   0.479   0.000  clkDiv_Madd__n0000_Mxor_Result<3>_Result1 (clkDiv__n0000<3>)
     FD:D                      0.176          clkDiv_3
    ----------------------------------------
    Total                      2.359ns (1.281ns logic, 1.078ns route)
                                       (54.3% logic, 45.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clkDiv_3:Q'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              1.572ns (Levels of Logic = 1)
  Source:            KD (PAD)
  Destination:       DFF1 (FF)
  Destination Clock: clkDiv_3:Q rising

  Data Path: KD to DFF1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.715   0.681  KD_IBUF (KD_IBUF)
     FD:D                      0.176          DFF1
    ----------------------------------------
    Total                      1.572ns (0.891ns logic, 0.681ns route)
                                       (56.7% logic, 43.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Offset:              6.216ns (Levels of Logic = 1)
  Source:            RDY_1 (FF)
  Destination:       RDY (PAD)
  Source Clock:      CLK rising

  Data Path: RDY_1 to RDY
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.626   0.681  RDY_1 (RDY_1)
     OBUF:I->O                 4.909          RDY_OBUF (RDY)
    ----------------------------------------
    Total                      6.216ns (5.535ns logic, 0.681ns route)
                                       (89.0% logic, 11.0% route)

=========================================================================
CPU : 6.41 / 6.89 s | Elapsed : 6.00 / 7.00 s
 
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Total memory usage is 102080 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    2 (   0 filtered)