keyboard.syr

游戏玩家通过控制PS/2键盘上的方向键

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: keyboard.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "keyboard.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "keyboard"
Output Format                      : NGC
Target Device                      : xc3s400-5-pq208

---- Source Options
Top Module Name                    : keyboard
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : keyboard.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/ASIC设计/zoumigong/keyboard.vhd" in Library work.
Entity <keyboard> compiled.
Entity <keyboard> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <keyboard> (Architecture <Behavioral>).
INFO:Xst:1739 - HDL ADVISOR - "D:/ASIC设计/zoumigong/keyboard.vhd" line 27: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <keyboard> analyzed. Unit <keyboard> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <keyboard>.
    Related source file is "D:/ASIC设计/zoumigong/keyboard.vhd".
    Found 1-bit register for signal <RDY>.
    Found 4-bit up counter for signal <clkDiv>.
    Found 1-bit register for signal <DFF1>.
    Found 1-bit register for signal <DFF2>.
    Found 1-bit register for signal <KCI>.
    Found 1-bit register for signal <KDI>.
    Found 8-bit register for signal <lastvalue>.
    Found 1-bit register for signal <receivedChar>.
    Found 3-bit shift register for signal <shiftRegSig1<8>>.
    Found 7-bit register for signal <shiftRegSig1<7:1>>.
    Found 4-bit shift register for signal <shiftRegSig2<8>>.
    Found 7-bit register for signal <shiftRegSig2<7:1>>.
    Found 8-bit register for signal <WaitReg>.
    Summary:
	inferred   1 Counter(s).
	inferred  36 D-type flip-flop(s).
	inferred   2 Shift register(s).
Unit <keyboard> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 4-bit up counter                  : 1
# Registers                        : 22
 1-bit register                    : 20
 8-bit register                    : 2
# Shift Registers                  : 2
 3-bit shift register              : 1
 4-bit shift register              : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <keyboard> ...
Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block keyboard, actual ratio is 0.
FlipFlop RDY has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : keyboard.ngr
Top Level Output File Name         : keyboard
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 12

Macro Statistics :
# Registers                        : 23
#      1-bit register              : 20
#      4-bit register              : 1
#      8-bit register              : 2
# Shift Registers                  : 2