📄 hwinit.c
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}
//-----------------------------------------------------------------------------
//
// Function: GetSysIntr
//
// This function is to return the SYSINTR value being used by OTG USB core
//
// Parameters:
// NONE
//
// Returns:
// SYSINTR being used
//
//-----------------------------------------------------------------------------
DWORD GetSysIntr(void)
{
return SYSINTR_USBOTG;
}
#if (USB_CLIENT_MODE == 1)
//---------------------------------------------------------------------------------------------
// Function: Reset
// - Resets USB otg
//
// Parameters:
// pRegs - Pointer to USB Registers
//
// Return:
// NULL
//------------------------------------------------------------------------------------------------
void Reset(CSP_USB_REGS *pRegs)
{
USB_USBCMD_T Cmd;
DWORD *temp;
UINT32 nAttempts = 0xFFFFFFFF;
temp = (DWORD *)&Cmd;
*temp = INREG32(&pRegs->OTG.USBCMD);
Cmd.RST = USBCMD_RESET;
OUTREG32(&pRegs->OTG.USBCMD, *temp);
while ((INREG32(&pRegs->OTG.USBCMD)& (USBCMD_RESET << USBCMD_RESET_LSH)) )
{
//RETAILMSG(1, (TEXT("USBCMD = 0x%x\r\n"), INREG32(&pRegs->OTG.USBCMD)));
Sleep(10);
}
}
//---------------------------------------------------------------------------------------------
// Function: Stop
// - Stops USB otg
//
// Parameters:
// pRegs - Pointer to USB Registers
//
// Return:
// NULL
//------------------------------------------------------------------------------------------------
void Stop(CSP_USB_REGS *pRegs)
{
USB_USBCMD_T Cmd;
DWORD *temp;
int nAttempts = 0;
temp = (DWORD *)&Cmd;
*temp = INREG32(&pRegs->OTG.USBCMD);
Cmd.RS = RS_STOP;
OUTREG32(&pRegs->OTG.USBCMD, *temp);
while (((INREG32(&pRegs->OTG.USBCMD) & 0x1) == 0x1) && (nAttempts++ < 50) )
{
//RETAILMSG(1, (TEXT("USBCMD= 0x%x\r\n"), (INREG32(&(*regs)->OTG.USBCMD))));
Sleep(10);
}
}
//---------------------------------------------------------------------------------------------
// Function: SetMode
// - Sets otg mode to host or device controller
//
// Parameters:
// pRegs - Pointer to USB Registers
//
// Return:
// NULL
//------------------------------------------------------------------------------------------------
void SetMode(CSP_USB_REGS *pRegs, UINT uCMMode)
{
USB_USBMODE_T Mode;
DWORD *temp;
temp = (DWORD *)&Mode;
*temp = INREG32(&pRegs->OTG.USBMODE);
Mode.CM = uCMMode;
if(uCMMode == CM_DEVICE_CONTROLLER)
{
Mode.SLOM = SLOM_LOCKOUT_OFF; // 2.3 hardware and later
}
OUTREG32(&pRegs->OTG.USBMODE, *temp);
Sleep(10);
if ((INREG32(&pRegs->OTG.USBMODE)& CM_HOST_CONTROLLER) != CM_HOST_CONTROLLER)
{
//RETAILMSG(1, (TEXT("USBMode setting failure\r\n")));
return;
}
}
//-----------------------------------------------------------------------------
//
// Function: InitializeCPLDHost
//
// This function is to configure the CPLD to FS USB Host
//
// Parameters:
// None
// Returns:
// TRUE: Success
// FALSE: Failure
//
//-----------------------------------------------------------------------------
static BOOL InitializeCPLDHost()
{
volatile PCSP_PBC_REGS cpld;
PHYSICAL_ADDRESS phyAddr;
phyAddr.QuadPart = BSP_BASE_REG_PA_PBC_BASE;
cpld = (PCSP_PBC_REGS) MmMapIoSpace(phyAddr, sizeof(CSP_PBC_REGS), FALSE);
if (cpld == NULL)
{
RETAILMSG(1,
(TEXT("%s(): MmMapIoSpace failed!\r\n"), __WFUNCTION__));
return FALSE;
}
//enble OTG
OUTREG16(&cpld->BCTRL3_SET,(1<<PBC_BCTRL3_USB_OTG_ON_LSH));
//enable VBUS
OUTREG16(&cpld->BCTRL3_CLEAR,(1<<PBC_BCTRL3_OTG_VBUS_EN_LSH));
MmUnmapIoSpace(cpld, sizeof(CSP_PBC_REGS));
return TRUE;
}
//-----------------------------------------------------------------------------
//
// Function: ConfigOTGFSHost
//
// This function is to configure FS host functionality on the USB OTG Core.
//
// Parameters:
// pRegs - Pointer to 3 USB Core Registers
//
// Returns:
// NULL
//
//-----------------------------------------------------------------------------
static void ConfigOTGFSHost(CSP_USB_REGS *pRegs)
{
USB_PORTSC_T Portsc;
USB_CTRL_T Ctrl;
DWORD *temp;
//RETAILMSG(1, (TEXT("ConfigOTGHost\r\n")));
//usb_otg_ulpi_interface_configure
temp = (DWORD *)&Portsc;
*temp = INREG32(&pRegs->OTG.PORTSC);
Portsc.LS = LS_J_STATE;
Portsc.PTS = PTS_SERIAL;
OUTREG32(&pRegs->OTG.PORTSC, *temp);
// usb_ulpi_interrupt_enable
temp = (DWORD *)&Ctrl;
*temp = INREG32(&pRegs->USB_CTRL);
Ctrl.OUIE = OUIE_INT_WAKE_IGNORE;
OUTREG32(&pRegs->USB_CTRL, *temp);
// Serial Interface config
temp = (DWORD *)&Ctrl;
*temp = INREG32(&pRegs->USB_CTRL);
Ctrl.OSIC = 0x1; //OWIE_INT_ENABLE;
OUTREG32(&pRegs->USB_CTRL, *temp);
// usb_otg_interrupt_enable
temp = (DWORD *)&Ctrl;
*temp = INREG32(&pRegs->USB_CTRL);
Ctrl.OWIE = OWIE_INT_ENABLE;
OUTREG32(&pRegs->USB_CTRL, *temp);
// usb_otg_power_mask_enable
temp = (DWORD *)&Ctrl;
*temp = INREG32(&pRegs->USB_CTRL);
Ctrl.OPM = OPM_NO_USBPWR;
OUTREG32(&pRegs->USB_CTRL, *temp);
// usb_bypass_inactive
temp = (DWORD *)&Ctrl;
*temp=0;
Ctrl.BPE = BPE_BYPASS_INACTIVE; // Bypass Enable bit, clear it
CLRREG32(&pRegs->USB_CTRL, *temp);
// otg_setmode
Reset(pRegs);
SetMode(pRegs,CM_HOST_CONTROLLER);
// otg_power_on_port1
if (INREG32(&pRegs->OTG.HCSPARAMS) &(0x1 << PPC_LSH))
{
DWORD Mask = (0x1<<1) + (0x1<<3)+(0x1<<5);
CLRREG32(&pRegs->OTG.PORTSC, Mask);
temp = (DWORD *)&Portsc;
*temp = INREG32(&pRegs->OTG.PORTSC);
Portsc.PP = PP_READ_WRITE;
OUTREG32(&pRegs->OTG.PORTSC, *temp);
}
else
RETAILMSG(1, (TEXT("Host does not control power\r\n")));
//otg_controller_reset
Reset(pRegs);
SetMode(pRegs,CM_HOST_CONTROLLER);
}
//-----------------------------------------------------------------------------
//
// Function: InitializeOTGHostTransceiver
//
// This function is to configure the OTG USB Core for FS OTG Host.
//
// Parameters:
// pRegs - Pointer to 3 USB Core Registers
//
// Returns:
// NULL
//
//-----------------------------------------------------------------------------
void InitializeOTGHostTransceiver(PCSP_USB_REGS* pRegs)
{
// Clear USB Interrupt enable registers
OUTREG32(&(*pRegs)->OTG.USBINTR, 0);
InitializeCPLDHost();
// Stop the controller first
{
USB_USBCMD_T Cmd;
USB_USBSTS_T Sts;
USB_USBMODE_T Mode;
DWORD * temp = (DWORD *)&Cmd;
DWORD * temp2 = (DWORD*)&Sts;
DWORD *pTmpMode = (DWORD*)&Mode;
int nAttempts = 0;
*temp = INREG32(&(*pRegs)->OTG.USBCMD);
Cmd.RS = 0;
OUTREG32(&(*pRegs)->OTG.USBCMD, *temp);
*pTmpMode = INREG32(&(*pRegs)->OTG.USBMODE);
if ( Mode.CM == 0x3 )
{
*temp2 = INREG32(&(*pRegs)->OTG.USBSTS);
while ( (Sts.HCH == 0) && (nAttempts++ < 50) )
{
Sleep(10);
*temp2 = INREG32(&(*pRegs)->OTG.USBSTS);
}
}
}
// Do a reset first no matter what
Reset(*pRegs);
// actually set the mode to HOST now
SetMode(*pRegs,CM_HOST_CONTROLLER);
ConfigOTGFSHost(*pRegs);
{ //usb_bypass_inactive()
USB_CTRL_T Ctrl;
DWORD * temp=(DWORD *)&Ctrl;
*temp=0;
Ctrl.BPE = BPE_BYPASS_ACTIVE; // Bypass Enable bit, clear it
CLRREG32(&(*pRegs)->USB_CTRL, *temp);
}
SetMode(*pRegs,CM_HOST_CONTROLLER);
//RETAILMSG(1, (TEXT("PowerOnPort\r\n")));
// power on port
{
DWORD *temp;
USB_HCSPARAMS_T Hcs;
temp=(DWORD *)&Hcs;
*temp=INREG32(&(*pRegs)->OTG.HCSPARAMS);
if (Hcs.PPC)
{
USB_PORTSC_T Portsc;
DWORD * temp2= (DWORD *)&Portsc;
*temp2 = INREG32(&(*pRegs)->OTG.PORTSC);
Portsc.PP = PP_READ_WRITE;
SETREG32(&(*pRegs)->OTG.PORTSC, *temp2);
}
}
// Last to do: Enable the ID Pin Interrupt in OTGSC
{
USB_OTGSC_T temp;
DWORD *t = (DWORD *)&temp;
*t = INREG32(&(*pRegs)->OTG.OTGSC);
temp.IDIE = 1;
OUTREG32(&(*pRegs)->OTG.OTGSC, *t);
}
}
#endif // #if (USB_CLIENT_MODE == 1)
#pragma optimize( "", on )
//------------------------------------------------------------------------------
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