viterbi_block_tb.vhd

来自「这是一个计算维特比译码的程序」· VHDL 代码 · 共 707 行 · 第 1/2 页

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END viterbi_block_tb_pkg;

-- -------------------------------------------------------------
--
-- Module: viterbi_block_tb
-- Simulink Path: hdlsrc
-- Created: 2009-03-24 16:24:20
-- Hierarchy Level: 1
--
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE work.viterbi_block_pkg.ALL;
USE work.viterbi_block_tb_pkg.ALL;

ENTITY viterbi_block_tb IS

END viterbi_block_tb;


ARCHITECTURE rtl OF viterbi_block_tb IS
  -- -------------------------------------------------------------
  -- Component Declarations
  -- -------------------------------------------------------------
  COMPONENT viterbi_block
   PORT( clk                             :   IN    std_logic; 
         reset                           :   IN    std_logic; 
         clk_enable                      :   IN    std_logic; 
         In1                             :   IN    vector_of_std_logic_vector2(0 TO 1); -- sfix6_En3
         ce_out                          :   OUT   std_logic; 
         Out1                            :   OUT   std_logic  
         );
  END COMPONENT; 

  -- -------------------------------------------------------------
  -- Component Configuration Statements
  -- -------------------------------------------------------------
  FOR ALL : viterbi_block
    USE ENTITY work.viterbi_block(rtl);

  -- Constants
  CONSTANT clk_high                         : time := 5 ns;
  CONSTANT clk_low                          : time := 5 ns;
  CONSTANT clk_period                       : time := 10 ns;
  CONSTANT clk_hold                         : time := 2 ns;
  CONSTANT clk_setup                        : time := 2 ns;
  CONSTANT clk2Q                            : time := 2 ns;
  CONSTANT delay                            : time := 2 ns;

  CONSTANT CLKRATE                        : integer := 1; -- uint32
  CONSTANT LATENCY                        : integer := 1; -- uint32
  CONSTANT NO_OF_TESTS                    : integer := 101; -- uint32
  CONSTANT MAX_TIMEOUT                    : integer := 2; -- uint32
  CONSTANT MAX_ERROR_COUNT                : integer := 101; -- uint32


  -- Signals
  SIGNAL clk                              : std_logic; -- boolean
  SIGNAL reset                            : std_logic; -- boolean
  SIGNAL clk_enable                       : std_logic; -- boolean
  SIGNAL In1                              : vector_of_std_logic_vector2(0 TO 1); -- sfix6_En3
  SIGNAL ce_out                           : std_logic; -- boolean
  SIGNAL Out1                             : std_logic; -- boolean

  SIGNAL txdataCnt                        : integer; -- uint32
  SIGNAL rxdataCnt                        : integer; -- uint32
  SIGNAL tb_enb                           : std_logic; -- boolean
  SIGNAL rdenb                            : std_logic; -- boolean
  SIGNAL srcDone                          : std_logic; -- boolean
  SIGNAL snkDone                          : std_logic; -- boolean
  SIGNAL GatewayIn_1_clk                  : std_logic; -- boolean
  SIGNAL GatewayIn_1_reset                : std_logic; -- boolean
  SIGNAL GatewayIn_1_rdenb                : std_logic; -- boolean
  SIGNAL GatewayIn_1_addr                 : unsigned(6 DOWNTO 0); -- ufix7
  SIGNAL GatewayIn_1_nxtaddr              : unsigned(6 DOWNTO 0); -- ufix7
  SIGNAL GatewayIn_1_done                 : std_logic; -- boolean
  SIGNAL Out1_timeout                     : integer; -- uint32
  SIGNAL Out1_errCnt                      : integer; -- uint32
  SIGNAL Out1_clk                         : std_logic; -- boolean
  SIGNAL Out1_reset                       : std_logic; -- boolean
  SIGNAL Out1_rdenb                       : std_logic; -- boolean
  SIGNAL Out1_addr                        : unsigned(6 DOWNTO 0); -- ufix7
  SIGNAL Out1_nxtaddr                     : unsigned(6 DOWNTO 0); -- ufix7
  SIGNAL Out1_done                        : std_logic; -- boolean
  SIGNAL Out1_ref                         : std_logic; -- boolean
  SIGNAL check1_Done                      : std_logic; -- boolean


BEGIN
  -- Component Instances
  u_viterbi_block: viterbi_block
    PORT MAP (
              clk                              => clk,
              reset                            => reset,
              clk_enable                       => clk_enable,
              In1                              => In1,
              ce_out                           => ce_out,
              Out1                             => Out1      );


  -- Block Statements
  -- -------------------------------------------------------------
  -- Driving the test bench enable
  -- -------------------------------------------------------------

  tb_enb_gen: PROCESS (clk,reset)
  BEGIN
    IF (reset = '1') THEN 
      tb_enb <= '0';
    ELSIF clk'event AND clk = '1' THEN
      tb_enb <= '1';
      IF snkDone = '1'  THEN
        tb_enb <= '0';
        ASSERT FALSE
          REPORT "**************TEST COMPLETED **************"
          SEVERITY NOTE;
      END IF;
    END IF;
  END PROCESS tb_enb_gen;

  -- -------------------------------------------------------------
  -- System Clock (fast clock) and reset
  -- -------------------------------------------------------------

  clk_gen: PROCESS
  BEGIN
    clk <= '1';
    WAIT FOR clk_high;
    clk <= '0';
    WAIT FOR clk_low;
    IF snkDone = '1' THEN
      clk <= '1';
      WAIT FOR clk_high;
      clk <= '0';
      WAIT;
    END IF;
  END PROCESS clk_gen;

  reset_gen: PROCESS
  BEGIN
    reset <= '1';
    WAIT FOR clk_period * 2 * CLKRATE + clk_hold;
    reset <= '0';
    WAIT;
  END PROCESS reset_gen;

  rdenb <= tb_enb WHEN snkDone =  '0' ELSE
           '0' AFTER clk_hold;

  clk_enable <= rdenb;

  -- -------------------------------------------------------------
  -- Read the data and transmit it to the DUT
  -- -------------------------------------------------------------

  GatewayIn_1_procedure (
    clk       => GatewayIn_1_clk,
    reset     => GatewayIn_1_reset,
    rdenb     => GatewayIn_1_rdenb,
    addr      => GatewayIn_1_addr,
    nxt_addr  => GatewayIn_1_nxtaddr,
    done      => GatewayIn_1_done);

  GatewayIn_1_rdenb <= rdenb;

  GatewayIn_1_clk <= clk;

  GatewayIn_1_reset <= reset;

  stimuli_1: PROCESS(GatewayIn_1_rdenb, GatewayIn_1_addr)
  BEGIN
    IF GatewayIn_1_rdenb = '1' THEN
      In1 <= GatewayIn_1_force(TO_INTEGER(GatewayIn_1_addr));
    ELSE
      In1 <= ( 'X','X');
    END IF;
  END PROCESS stimuli_1;

  -- -------------------------------------------------------------
  -- Create done signal for Input data
  -- -------------------------------------------------------------

  srcDone <= GatewayIn_1_done;

  -- -------------------------------------------------------------
  --  Checker: Checking the received data from the DUT.
  -- -------------------------------------------------------------

  Out1_procedure (
    clk       => Out1_clk,
    reset     => Out1_reset,
    rdenb     => Out1_rdenb,
    addr      => Out1_addr,
    nxt_addr  => Out1_nxtaddr,
    done      => Out1_done);

  Out1_rdenb <= ce_out;

  Out1_clk <= clk;

  Out1_reset <= reset;

  checker_1: PROCESS(clk, reset)
  BEGIN
    IF reset = '1' THEN
      Out1_timeout <= 0;
      Out1_errCnt <= 0;
      Out1_ref <= Out1_expected(TO_INTEGER(Out1_nxtaddr));
    ELSIF clk'event and clk ='1' THEN
      IF Out1_rdenb = '1' THEN
        Out1_timeout <= 0;
        Out1_ref <= Out1_expected(TO_INTEGER(Out1_nxtaddr));
        IF Out1 /= Out1_expected(TO_INTEGER(Out1_addr)) THEN
          Out1_errCnt <= Out1_errCnt + 1;
          ASSERT FALSE 
            REPORT "Error in Out1: Expected " 
            & to_hex(Out1_expected(TO_INTEGER(Out1_addr)))
            & " Actual "
            & to_hex(Out1)
            SEVERITY ERROR;
          IF Out1_errCnt >= MAX_ERROR_COUNT THEN
            ASSERT FALSE
              REPORT "Number of errors exceed the maximum error"
              SEVERITY Warning;
          END IF;
        END IF;
      ELSIF Out1_timeout > MAX_TIMEOUT THEN
        Out1_errCnt <= Out1_errCnt + 1;
        ASSERT FALSE
          REPORT "Timeout: Data is not received after timeout."
          SEVERITY FAILURE ;
      ELSE
        Out1_timeout <= Out1_timeout + 1 ;
      END IF;
    END IF;
  END PROCESS checker_1;
  checkDone_1: PROCESS(clk, reset)
  BEGIN
    IF reset = '1' THEN
      check1_Done <= '0';
    ELSIF clk'event and clk ='1' THEN
      IF check1_Done = '0' AND Out1_done = '1' AND Out1_rdenb = '1' THEN
        check1_Done <= '1';
      END IF;
    END IF;
  END PROCESS checkDone_1;
  -- -------------------------------------------------------------
  -- Create done signal for output data
  -- -------------------------------------------------------------

  snkDone <= check1_Done;

  -- Assignment Statements



END rtl;