acs.vhd

这是一个计算维特比译码的程序

  SIGNAL Demux5_out3                      : vector_of_unsigned4(0 TO 3);  
  SIGNAL Demux5_out4                      : vector_of_unsigned4(0 TO 3);  
  SIGNAL s_9                              : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem8_out1                  : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem8_out2                  : std_logic_vector(0 TO 3);  -- boolean [4]
  SIGNAL s_10                             : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem9_out1                  : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem9_out2                  : std_logic_vector(0 TO 3);  -- boolean [4]
  SIGNAL s_11                             : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem10_out1                 : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem10_out2                 : std_logic_vector(0 TO 3);  -- boolean [4]
  SIGNAL s_12                             : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem11_out1                 : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem11_out2                 : std_logic_vector(0 TO 3);  -- boolean [4]
  SIGNAL Mux5_out1                        : std_logic_vector(0 TO 15);  -- boolean [16]
  SIGNAL Demux6_out1                      : vector_of_unsigned4(0 TO 3);  
  SIGNAL Demux6_out2                      : vector_of_unsigned4(0 TO 3);  
  SIGNAL Demux6_out3                      : vector_of_unsigned4(0 TO 3);  
  SIGNAL Demux6_out4                      : vector_of_unsigned4(0 TO 3);  
  SIGNAL s_13                             : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem12_out1                 : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem12_out2                 : std_logic_vector(0 TO 3);  -- boolean [4]
  SIGNAL s_14                             : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem13_out1                 : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem13_out2                 : std_logic_vector(0 TO 3);  -- boolean [4]
  SIGNAL s_15                             : vector_of_std_logic_vector4(0 TO 3); 
  SIGNAL Subsystem14_out1                 : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem14_out2                 : std_logic_vector(0 TO 3);  -- boolean [4]
  SIGNAL s_16                             : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem15_out1                 : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem15_out2                 : std_logic_vector(0 TO 3);  -- boolean [4]
  SIGNAL Mux7_out1                        : std_logic_vector(0 TO 15);  -- boolean [16]
  SIGNAL Mux9_out1                        : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL s_17                             : vector_of_unsigned4(0 TO 3);  
  SIGNAL s_18                             : vector_of_unsigned4(0 TO 3);  
  SIGNAL s_19                             : vector_of_unsigned4(0 TO 3);  
  SIGNAL s_20                             : vector_of_unsigned4(0 TO 3);  
  SIGNAL Mux_out1                         : vector_of_unsigned4(0 TO 15);  
  SIGNAL s_21                             : vector_of_unsigned4(0 TO 3);  
  SIGNAL s_22                             : vector_of_unsigned4(0 TO 3);  
  SIGNAL s_23                             : vector_of_unsigned4(0 TO 3);  
  SIGNAL s_24                             : vector_of_unsigned4(0 TO 3);  
  SIGNAL Mux2_out1                        : vector_of_unsigned4(0 TO 15); 
  SIGNAL s_25                             : vector_of_unsigned4(0 TO 3);  
  SIGNAL s_26                             : vector_of_unsigned4(0 TO 3);  
  SIGNAL s_27                             : vector_of_unsigned4(0 TO 3);  
  SIGNAL s_28                             : vector_of_unsigned4(0 TO 3);  
  SIGNAL Mux4_out1                        : vector_of_unsigned4(0 TO 15);  
  SIGNAL s_29                             : vector_of_unsigned4(0 TO 3);  
  SIGNAL s_30                             : vector_of_unsigned4(0 TO 3); 
  SIGNAL s_31                             : vector_of_unsigned4(0 TO 3);  
  SIGNAL s_32                             : vector_of_unsigned4(0 TO 3);  
  SIGNAL Mux6_out1                        : vector_of_unsigned4(0 TO 15);  
  SIGNAL Mux8_out1                        :vector_of_unsigned4(0 TO 63);  

BEGIN
  u_Subsystem : Subsystem
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       SM => s_1,  
       BM => BM,  
       NSM => Subsystem_out1,  
       DEC => Subsystem_out2  
       );

  u_Subsystem1 : Subsystem1
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       SM => s_2,  
       BM => BM,  
       NSM => Subsystem1_out1,  
       DEC => Subsystem1_out2  
       );

  u_Subsystem2 : Subsystem2
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       SM => s_3,  
       BM => BM,  
       NSM => Subsystem2_out1,  
       DEC => Subsystem2_out2  
       );

  u_Subsystem3 : Subsystem3
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       SM => s_4,  
       BM => BM,  
       NSM => Subsystem3_out1,  
       DEC => Subsystem3_out2  
       );

  u_Subsystem4 : Subsystem4
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       SM => s_5,  
       BM => BM,  
       NSM => Subsystem4_out1, 
       DEC => Subsystem4_out2  
       );

  u_Subsystem5 : Subsystem5
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       SM => s_6,  
       BM => BM,  
       NSM => Subsystem5_out1,  
       DEC => Subsystem5_out2  
       );

  u_Subsystem6 : Subsystem6
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       SM => s_7,  
       BM => BM,  
       NSM => Subsystem6_out1, 
       DEC => Subsystem6_out2  
       );

  u_Subsystem7 : Subsystem7
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       SM => s_8,  
       BM => BM,  
       NSM => Subsystem7_out1,  
       DEC => Subsystem7_out2  
       );

  u_Subsystem8 : Subsystem8
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       SM => s_9,  
       BM => BM,  
       NSM => Subsystem8_out1,  
       DEC => Subsystem8_out2  
       );

  u_Subsystem9 : Subsystem9
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       SM => s_10, 
       BM => BM,  
       NSM => Subsystem9_out1,  
       DEC => Subsystem9_out2  
       );

  u_Subsystem10 : Subsystem10
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       SM => s_11,  
       BM => BM,  
       NSM => Subsystem10_out1,  
       DEC => Subsystem10_out2  
       );

  u_Subsystem11 : Subsystem11
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       SM => s_12,  
       BM => BM,  
       NSM => Subsystem11_out1,  
       DEC => Subsystem11_out2  
       );

  u_Subsystem12 : Subsystem12
    PORT MAP
      (clk => clk,
       reset => reset, 
       enb => enb,
       SM => s_13,  
       BM => BM,  
       NSM => Subsystem12_out1,  
       DEC => Subsystem12_out2 
       );

  u_Subsystem13 : Subsystem13
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       SM => s_14,  
       BM => BM,  
       NSM => Subsystem13_out1,  
       DEC => Subsystem13_out2  
       );

  u_Subsystem14 : Subsystem14
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       SM => s_15,  
       BM => BM,  
       NSM => Subsystem14_out1,  
       DEC => Subsystem14_out2  
       );

  u_Subsystem15 : Subsystem15
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       SM => s_16,  
       BM => BM,  
       NSM => Subsystem15_out1,  
       DEC => Subsystem15_out2  
       );
  outputgen33: FOR k IN 0 TO 63 GENERATE
    s(k) <= SM(k);
  END GENERATE;

  Demux2_out1(0 TO 15) <= s(0 TO 15);

  Demux2_out2(0 TO 15) <= s(16 TO 31);

  Demux2_out3(0 TO 15) <= s(32 TO 47);

  Demux2_out4(0 TO 15) <= s(48 TO 63);



  Demux1_out1(0 TO 3) <= Demux2_out1(0 TO 3);

  Demux1_out2(0 TO 3) <= Demux2_out1(4 TO 7);

  Demux1_out3(0 TO 3) <= Demux2_out1(8 TO 11);

  Demux1_out4(0 TO 3) <= Demux2_out1(12 TO 15);



  outputgen32: FOR k IN 0 TO 3 GENERATE
    s_1(k) <= std_logic_vector(Demux1_out1(k));
  END GENERATE;

  outputgen31: FOR k IN 0 TO 3 GENERATE
    s_2(k) <= std_logic_vector(Demux1_out2(k));
  END GENERATE;

  outputgen30: FOR k IN 0 TO 3 GENERATE
    s_3(k) <= std_logic_vector(Demux1_out3(k));
  END GENERATE;

  outputgen29: FOR k IN 0 TO 3 GENERATE
    s_4(k) <= std_logic_vector(Demux1_out4(k));
  END GENERATE;

  Mux1_out1_1_gen:FOR k IN 0 TO 3 GENERATE
    Mux1_out1(k) <= Subsystem_out2(k);
  END GENERATE;

  Mux1_out1_2_gen:FOR k IN 0 TO 3 GENERATE
    Mux1_out1(k+4) <= Subsystem1_out2(k);
  END GENERATE;

  Mux1_out1_3_gen:FOR k IN 0 TO 3 GENERATE
    Mux1_out1(k+8) <= Subsystem2_out2(k);
  END GENERATE;

  Mux1_out1_4_gen:FOR k IN 0 TO 3 GENERATE
    Mux1_out1(k+12) <= Subsystem3_out2(k);
  END GENERATE;



  Demux4_out1(0 TO 3) <= Demux2_out2(0 TO 3);

  Demux4_out2(0 TO 3) <= Demux2_out2(4 TO 7);

  Demux4_out3(0 TO 3) <= Demux2_out2(8 TO 11);

  Demux4_out4(0 TO 3) <= Demux2_out2(12 TO 15);



  outputgen28: FOR k IN 0 TO 3 GENERATE
    s_5(k) <= std_logic_vector(Demux4_out1(k));
  END GENERATE;