decrement_stored_integer.vhd

这是一个计算维特比译码的程序

-- -------------------------------------------------------------
--
-- Module: Decrement_Stored_Integer
-- Simulink Path: hdlcoderviterbi/viterbi_block/Traceback/Decrement Stored Integer
-- Created: 2009-03-24 16:23:51
-- Hierarchy Level: 2
--
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY Decrement_Stored_Integer IS
  PORT( clk                               :   IN    std_logic;
        reset                             :   IN    std_logic;
        enb                               :   IN    std_logic;
        u                                 :   IN    std_logic_vector(7 DOWNTO 0);   
        y                                 :   OUT   std_logic_vector(7 DOWNTO 0)   
        );
END Decrement_Stored_Integer;


ARCHITECTURE rtl OF Decrement_Stored_Integer IS

  -- Signals
  SIGNAL s                                : unsigned(7 DOWNTO 0);  -- uint8
  SIGNAL FixPt_Constant_out1              : unsigned(7 DOWNTO 0);  -- uint8
  SIGNAL FixPt_Gateway_In_out1            : unsigned(7 DOWNTO 0);  -- uint8
  SIGNAL FixPt_Sum1_out1                  : unsigned(7 DOWNTO 0);  -- uint8
  SIGNAL FixPt_Gateway_In_tmp             : unsigned(7 DOWNTO 0);   
  SIGNAL sub_cast                         : unsigned(7 DOWNTO 0);   
  SIGNAL sub_cast_1                       : unsigned(7 DOWNTO 0);   
  SIGNAL sub_temp                         : unsigned(8 DOWNTO 0);  -- uint9

BEGIN
  s <= unsigned(u);

  FixPt_Constant_out1 <= to_unsigned(1, 8);


  FixPt_Gateway_In_tmp <= FixPt_Constant_out1;

  FixPt_Gateway_In_out1 <= FixPt_Gateway_In_tmp;


  sub_cast <= s;
  sub_cast_1 <= FixPt_Gateway_In_out1;
  sub_temp <= resize(sub_cast, 9) - resize(sub_cast_1, 9);
  FixPt_Sum1_out1 <= sub_temp(7 DOWNTO 0);


  y <= std_logic_vector(FixPt_Sum1_out1);



END rtl;