bmc_unit.vhd

这是一个计算维特比译码的程序

-- -------------------------------------------------------------
--
-- Module: BMC_Unit
-- Simulink Path: hdlcoderviterbi/viterbi_block/BMC Unit
-- Created: 2009-03-24 16:23:51
-- Hierarchy Level: 1
--
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.viterbi_block_pkg.ALL;
use IEEE.std_logic_unsigned.all;

ENTITY BMC_Unit IS
  PORT( clk                               :   IN    std_logic;
        reset                             :   IN    std_logic;
        enb                               :   IN    std_logic;
        In1                               :   IN    vector_of_std_logic_vector2(0 TO 1);  -- Indata
        Out1                              :   OUT   vector_of_std_logic_vector4(0 TO 3)    
        );
END BMC_Unit;


ARCHITECTURE rtl OF BMC_Unit IS

-- Local Type Definitions
  
  SIGNAL cons_compare  : std_logic_vector(0 to 1);
  SIGNAL cons_compare1 : std_logic_vector(0 to 1);
  SIGNAL cons_compare2 : std_logic_vector(0 to 1);
  SIGNAL cons_compare3 : std_logic_vector(0 to 1);
  signal s: std_logic_vector(0 to 1);
  SIGNAL temp_out: vector_of_std_logic_vector4(0 TO 3);
  signal count_temp : std_logic_vector(7 downto 0);
BEGIN
--four banch of decoder   
  cons_compare  <="00";
  cons_compare1 <="01";
  cons_compare2 <="10";
  cons_compare3 <="11";

process(clk)
variable count : integer;
begin
if reset='1' then 
 count :=0;
 count_temp <=(others =>'0');
elsif clk'event and clk='1' then 
   if count=100 then
        count :=0;
         count_temp <=(others =>'0');
   else
        count:=count+1;
        count_temp <=count_temp+'1';
   end if;
 end if;
 end process;
    
     
outputgen1: FOR k IN 0 TO 1 GENERATE
    s(k) <= In1(k);
 END GENERATE;
----the hanmmin distance of hard decision
    temp_out(0) <= ("000"&(s(0) xor '0'))+("000"&(s(1) xor '0')) ;
    temp_out(1) <= ("000"&(s(0) xor '0'))+("000"&(s(1) xor '1')) ;
    temp_out(2) <= ("000"&(s(0) xor '1'))+("000"&(s(1) xor '0')) ;
    temp_out(3) <= ("000"&(s(0) xor '1'))+("000"&(s(1) xor '1')) ;


 outputgen: FOR k IN 0 TO 3 GENERATE
    Out1(k) <= temp_out(k);
 END GENERATE;

END rtl;