traceback.vhd

这是一个计算维特比译码的程序

  u_Subsystem6 : Subsystem6_entity1
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem5_out1,  -- boolean [64]
       In2 => Subsystem5_out2,  
       Out1 => Subsystem6_out1,  -- boolean [64]
       Out2 => Subsystem6_out2  
       );

  u_Subsystem7 : Subsystem7_entity1
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem6_out1,  -- boolean [64]
       In2 => Subsystem6_out2,  
       Out1 => Subsystem7_out1,  -- boolean [64]
       Out2 => Subsystem7_out2  
       );

  u_Subsystem8 : Subsystem8_entity1
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem7_out1,  -- boolean [64]
       In2 => Subsystem7_out2,  
       Out1 => Subsystem8_out1,  -- boolean [64]
       Out2 => Subsystem8_out2  
       );

  u_Subsystem9 : Subsystem9_entity1
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem8_out1,  -- boolean [64]
       In2 => Subsystem8_out2,  
       Out1 => Subsystem9_out1,  -- boolean [64]
       Out2 => Subsystem9_out2  
       );

  u_Subsystem10 : Subsystem10_entity1
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem9_out1,  -- boolean [64]
       In2 => Subsystem9_out2,  
       Out1 => Subsystem10_out1,  -- boolean [64]
       Out2 => Subsystem10_out2  
       );

  u_Subsystem11 : Subsystem11_entity1
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem10_out1,  -- boolean [64]
       In2 => Subsystem10_out2,  
       Out1 => Subsystem11_out1,  -- boolean [64]
       Out2 => Subsystem11_out2  
       );

  u_Subsystem12 : Subsystem12_entity1
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem11_out1,  -- boolean [64]
       In2 => Subsystem11_out2,  
       Out1 => Subsystem12_out1,  -- boolean [64]
       Out2 => Subsystem12_out2  
       );

  u_Subsystem13 : Subsystem13_entity1
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem12_out1,  -- boolean [64]
       In2 => Subsystem12_out2,  
       Out1 => Subsystem13_out1,  -- boolean [64]
       Out2 => Subsystem13_out2  
       );

  u_Subsystem14 : Subsystem14_entity1
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem13_out1,  -- boolean [64]
       In2 => Subsystem13_out2,  
       Out1 => Subsystem14_out1,  -- boolean [64]
       Out2 => Subsystem14_out2  
       );

  u_Subsystem15 : Subsystem15_entity1
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem14_out1,  -- boolean [64]
       In2 => Subsystem14_out2,  
       Out1 => Subsystem15_out1,  -- boolean [64]
       Out2 => Subsystem15_out2  
       );

  u_Subsystem16 : Subsystem16
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem15_out1,  -- boolean [64]
       In2 => Subsystem15_out2,  
       Out1 => Subsystem16_out1,  -- boolean [64]
       Out2 => Subsystem16_out2  
       );

  u_Subsystem17 : Subsystem17
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem16_out1,  -- boolean [64]
       In2 => Subsystem16_out2,  
       Out1 => Subsystem17_out1,  -- boolean [64]
       Out2 => Subsystem17_out2  
       );

  u_Subsystem18 : Subsystem18
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem17_out1,  -- boolean [64]
       In2 => Subsystem17_out2,  
       Out1 => Subsystem18_out1,  -- boolean [64]
       Out2 => Subsystem18_out2  
       );

  u_Subsystem19 : Subsystem19
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem18_out1,  -- boolean [64]
       In2 => Subsystem18_out2,  
       Out1 => Subsystem19_out1,  -- boolean [64]
       Out2 => Subsystem19_out2  
       );

  u_Subsystem20 : Subsystem20
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem19_out1,  -- boolean [64]
       In2 => Subsystem19_out2,  
       Out1 => Subsystem20_out1,  -- boolean [64]
       Out2 => Subsystem20_out2  
       );

  u_Subsystem21 : Subsystem21
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem20_out1,  -- boolean [64]
       In2 => Subsystem20_out2,  
       Out1 => Subsystem21_out1,  -- boolean [64]
       Out2 => Subsystem21_out2  
       );

  u_Subsystem22 : Subsystem22
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem21_out1,  -- boolean [64]
       In2 => Subsystem21_out2,  
       Out1 => Subsystem22_out1,  -- boolean [64]
       Out2 => Subsystem22_out2  
       );

  u_Subsystem23 : Subsystem23
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem22_out1,  -- boolean [64]
       In2 => Subsystem22_out2,  
       Out1 => Subsystem23_out1,  -- boolean [64]
       Out2 => Subsystem23_out2  
       );

  u_Subsystem24 : Subsystem24
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem23_out1,  -- boolean [64]
       In2 => Subsystem23_out2,  
       Out1 => Subsystem24_out1,  -- boolean [64]
       Out2 => Subsystem24_out2  
       );

  u_Subsystem25 : Subsystem25
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem24_out1,  -- boolean [64]
       In2 => Subsystem24_out2,  
       Out1 => Subsystem25_out1,  -- boolean [64]
       Out2 => Subsystem25_out2  
       );

  u_Subsystem26 : Subsystem26
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem25_out1,  -- boolean [64]
       In2 => Subsystem25_out2,  
       Out1 => Subsystem26_out1,  -- boolean [64]
       Out2 => Subsystem26_out2  
       );

  u_Subsystem27 : Subsystem27
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem26_out1,  -- boolean [64]
       In2 => Subsystem26_out2,  
       Out1 => Subsystem27_out1,  -- boolean [64]
       Out2 => Subsystem27_out2  
       );
  Reshape_out1_gen:FOR k IN 0 TO 63 GENERATE
    Reshape_out1(k) <= In1(k);
  END GENERATE;


  s <= unsigned(Subsystem27_out2);

  Bitwise_AND_with_Mask_out1 <=  s AND Bitwise_AND_with_Mask_const;


  Data_Type_Conversion_out1 <= '1' WHEN Bitwise_AND_with_Mask_out1(7 DOWNTO 1) /= "0000000"
      ELSE Bitwise_AND_with_Mask_out1(0);


  Unit_Delay_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay_out1 <= '0';
    ELSIF clk'event AND clk = '1' THEN
      IF enb = '1' THEN
        Unit_Delay_out1 <= Data_Type_Conversion_out1;
      END IF;
    END IF; 
  END PROCESS Unit_Delay_process;


  Out1 <= Unit_Delay_out1;


END rtl;