traceback.vhd

这是一个计算维特比译码的程序

          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem23
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem24
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem25
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem26
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem27
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  -- Component Configuration Statements
  FOR ALL : Decrement_Stored_Integer
    USE ENTITY work.Decrement_Stored_Integer(rtl);

  FOR ALL : Subsystem1_entity1
    USE ENTITY work.Subsystem1_entity1(rtl);

  FOR ALL : Subsystem2_entity1
    USE ENTITY work.Subsystem2_entity1(rtl);

  FOR ALL : Subsystem3_entity1
    USE ENTITY work.Subsystem3_entity1(rtl);

  FOR ALL : Subsystem4_entity1
    USE ENTITY work.Subsystem4_entity1(rtl);

  FOR ALL : Subsystem5_entity1
    USE ENTITY work.Subsystem5_entity1(rtl);

  FOR ALL : Subsystem6_entity1
    USE ENTITY work.Subsystem6_entity1(rtl);

  FOR ALL : Subsystem7_entity1
    USE ENTITY work.Subsystem7_entity1(rtl);

  FOR ALL : Subsystem8_entity1
    USE ENTITY work.Subsystem8_entity1(rtl);

  FOR ALL : Subsystem9_entity1
    USE ENTITY work.Subsystem9_entity1(rtl);

  FOR ALL : Subsystem10_entity1
    USE ENTITY work.Subsystem10_entity1(rtl);

  FOR ALL : Subsystem11_entity1
    USE ENTITY work.Subsystem11_entity1(rtl);

  FOR ALL : Subsystem12_entity1
    USE ENTITY work.Subsystem12_entity1(rtl);

  FOR ALL : Subsystem13_entity1
    USE ENTITY work.Subsystem13_entity1(rtl);

  FOR ALL : Subsystem14_entity1
    USE ENTITY work.Subsystem14_entity1(rtl);

  FOR ALL : Subsystem15_entity1
    USE ENTITY work.Subsystem15_entity1(rtl);

  FOR ALL : Subsystem16
    USE ENTITY work.Subsystem16(rtl);

  FOR ALL : Subsystem17
    USE ENTITY work.Subsystem17(rtl);

  FOR ALL : Subsystem18
    USE ENTITY work.Subsystem18(rtl);

  FOR ALL : Subsystem19
    USE ENTITY work.Subsystem19(rtl);

  FOR ALL : Subsystem20
    USE ENTITY work.Subsystem20(rtl);

  FOR ALL : Subsystem21
    USE ENTITY work.Subsystem21(rtl);

  FOR ALL : Subsystem22
    USE ENTITY work.Subsystem22(rtl);

  FOR ALL : Subsystem23
    USE ENTITY work.Subsystem23(rtl);

  FOR ALL : Subsystem24
    USE ENTITY work.Subsystem24(rtl);

  FOR ALL : Subsystem25
    USE ENTITY work.Subsystem25(rtl);

  FOR ALL : Subsystem26
    USE ENTITY work.Subsystem26(rtl);

  FOR ALL : Subsystem27
    USE ENTITY work.Subsystem27(rtl);

  -- Constants
  CONSTANT Bitwise_AND_with_Mask_const    : unsigned(7 DOWNTO 0) := to_unsigned(1, 8);  -- uint8

  -- Signals
  SIGNAL Reshape_out1                     : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Decrement_Stored_Integer_out1    : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem1_out1                  : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem1_out2                  : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem2_out1                  : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem2_out2                  : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem3_out1                  : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem3_out2                  : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem4_out1                  : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem4_out2                  : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem5_out1                  : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem5_out2                  : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem6_out1                  : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem6_out2                  : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem7_out1                  : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem7_out2                  : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem8_out1                  : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem8_out2                  : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem9_out1                  : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem9_out2                  : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem10_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem10_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem11_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem11_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem12_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem12_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem13_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem13_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem14_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem14_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem15_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem15_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem16_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem16_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem17_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem17_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem18_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem18_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem19_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem19_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem20_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem20_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem21_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem21_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem22_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem22_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem23_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem23_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem24_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem24_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem25_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem25_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem26_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem26_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Subsystem27_out1                 : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Subsystem27_out2                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL s                                : unsigned(7 DOWNTO 0);  -- uint8
  SIGNAL Bitwise_AND_with_Mask_out1       : unsigned(7 DOWNTO 0);  -- uint8
  SIGNAL Data_Type_Conversion_out1        : std_logic;
  SIGNAL Unit_Delay_out1                  : std_logic;

BEGIN
  u_Decrement_Stored_Integer : Decrement_Stored_Integer
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       u => In2,  
       y => Decrement_Stored_Integer_out1  
       );

  u_Subsystem1 : Subsystem1_entity1
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Reshape_out1,  -- boolean [64]
       In2 => Decrement_Stored_Integer_out1,  
       Out1 => Subsystem1_out1,  -- boolean [64]
       Out2 => Subsystem1_out2  
       );

  u_Subsystem2 : Subsystem2_entity1
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem1_out1,  -- boolean [64]
       In2 => Subsystem1_out2,  
       Out1 => Subsystem2_out1,  -- boolean [64]
       Out2 => Subsystem2_out2  
       );

  u_Subsystem3 : Subsystem3_entity1
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem2_out1,  -- boolean [64]
       In2 => Subsystem2_out2,  
       Out1 => Subsystem3_out1,  -- boolean [64]
       Out2 => Subsystem3_out2  
       );

  u_Subsystem4 : Subsystem4_entity1
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem3_out1,  -- boolean [64]
       In2 => Subsystem3_out2,  
       Out1 => Subsystem4_out1,  -- boolean [64]
       Out2 => Subsystem4_out2  
       );

  u_Subsystem5 : Subsystem5_entity1
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Subsystem4_out1,  -- boolean [64]
       In2 => Subsystem4_out2,  
       Out1 => Subsystem5_out1,  -- boolean [64]
       Out2 => Subsystem5_out2  
       );