traceback.vhd

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-- -------------------------------------------------------------
--
-- Module: Traceback
-- Simulink Path: hdlcoderviterbi/viterbi_block/Traceback
-- Created: 2009-03-24 16:24:10
-- Hierarchy Level: 1
--
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY Traceback IS
  PORT( clk                               :   IN    std_logic;
        reset                             :   IN    std_logic;
        enb                               :   IN    std_logic;
        In1                               :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
        In2                               :   IN    std_logic_vector(7 DOWNTO 0);  
        Out1                              :   OUT   std_logic
        );
END Traceback;


ARCHITECTURE rtl OF Traceback IS

  -- Component Declarations
  COMPONENT Decrement_Stored_Integer
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          u                               :   IN    std_logic_vector(7 DOWNTO 0);  
          y                               :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem1_entity1
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem2_entity1
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem3_entity1
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem4_entity1
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem5_entity1
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem6_entity1
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem7_entity1
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem8_entity1
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem9_entity1
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem10_entity1
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem11_entity1
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem12_entity1
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem13_entity1
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem14_entity1
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem15_entity1
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem16
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem17
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem18
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem19
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem20
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem21
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          Out2                            :   OUT   std_logic_vector(7 DOWNTO 0)  
          );
  END COMPONENT;

  COMPONENT Subsystem22
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    std_logic_vector(0 TO 63);  -- boolean [64]
          In2                             :   IN    std_logic_vector(7 DOWNTO 0);  
          Out1                            :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]