reorder.vhd

这是一个计算维特比译码的程序

-- -------------------------------------------------------------
--
-- Module: Reorder
-- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit/Reorder
-- Created: 2009-03-24 16:23:49
-- Hierarchy Level: 2
--
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.viterbi_block_pkg.ALL;

ENTITY Reorder IS
  PORT( clk                               :   IN    std_logic;
        reset                             :   IN    std_logic;
        enb                              :   IN    std_logic;
        IN_1                              :   IN    vector_of_std_logic_vector4(0 TO 63);  
        OUT_1                             :   OUT   vector_of_std_logic_vector4(0 TO 63)  
        );
END Reorder;


ARCHITECTURE rtl OF Reorder IS

  -- Local Type Definitions
  TYPE vector_of_unsigned4 IS ARRAY (NATURAL RANGE <>) OF std_logic_vector(3 DOWNTO 0);

  -- Signals
  SIGNAL s                                : vector_of_unsigned4(0 TO 63);  
  SIGNAL Convert_1_D_to_2_D_out1          : vector_of_unsigned4(0 TO 63);  
  SIGNAL Selector_out1                    : vector_of_unsigned4(0 TO 63);  
  SIGNAL Reshape_out1                     : vector_of_unsigned4(0 TO 63);  

BEGIN
  outputgen1: FOR k IN 0 TO 63 GENERATE
    s(k) <= IN_1(k);
  END GENERATE;

  Convert_1_D_to_2_D_out1_gen:FOR k IN 0 TO 63 GENERATE
    Convert_1_D_to_2_D_out1(k) <= s(k);
  END GENERATE;


  Selector_out1(0) <= Convert_1_D_to_2_D_out1(0);
  Selector_out1(1) <= Convert_1_D_to_2_D_out1(2);
  Selector_out1(2) <= Convert_1_D_to_2_D_out1(4);
  Selector_out1(3) <= Convert_1_D_to_2_D_out1(6);
  Selector_out1(4) <= Convert_1_D_to_2_D_out1(8);
  Selector_out1(5) <= Convert_1_D_to_2_D_out1(10);
  Selector_out1(6) <= Convert_1_D_to_2_D_out1(12);
  Selector_out1(7) <= Convert_1_D_to_2_D_out1(14);
  Selector_out1(8) <= Convert_1_D_to_2_D_out1(16);
  Selector_out1(9) <= Convert_1_D_to_2_D_out1(18);
  Selector_out1(10) <= Convert_1_D_to_2_D_out1(20);
  Selector_out1(11) <= Convert_1_D_to_2_D_out1(22);
  Selector_out1(12) <= Convert_1_D_to_2_D_out1(24);
  Selector_out1(13) <= Convert_1_D_to_2_D_out1(26);
  Selector_out1(14) <= Convert_1_D_to_2_D_out1(28);
  Selector_out1(15) <= Convert_1_D_to_2_D_out1(30);
  Selector_out1(16) <= Convert_1_D_to_2_D_out1(32);
  Selector_out1(17) <= Convert_1_D_to_2_D_out1(34);
  Selector_out1(18) <= Convert_1_D_to_2_D_out1(36);
  Selector_out1(19) <= Convert_1_D_to_2_D_out1(38);
  Selector_out1(20) <= Convert_1_D_to_2_D_out1(40);
  Selector_out1(21) <= Convert_1_D_to_2_D_out1(42);
  Selector_out1(22) <= Convert_1_D_to_2_D_out1(44);
  Selector_out1(23) <= Convert_1_D_to_2_D_out1(46);
  Selector_out1(24) <= Convert_1_D_to_2_D_out1(48);
  Selector_out1(25) <= Convert_1_D_to_2_D_out1(50);
  Selector_out1(26) <= Convert_1_D_to_2_D_out1(52);
  Selector_out1(27) <= Convert_1_D_to_2_D_out1(54);
  Selector_out1(28) <= Convert_1_D_to_2_D_out1(56);
  Selector_out1(29) <= Convert_1_D_to_2_D_out1(58);
  Selector_out1(30) <= Convert_1_D_to_2_D_out1(60);
  Selector_out1(31) <= Convert_1_D_to_2_D_out1(62);
  Selector_out1(32) <= Convert_1_D_to_2_D_out1(1);
  Selector_out1(33) <= Convert_1_D_to_2_D_out1(3);
  Selector_out1(34) <= Convert_1_D_to_2_D_out1(5);
  Selector_out1(35) <= Convert_1_D_to_2_D_out1(7);
  Selector_out1(36) <= Convert_1_D_to_2_D_out1(9);
  Selector_out1(37) <= Convert_1_D_to_2_D_out1(11);
  Selector_out1(38) <= Convert_1_D_to_2_D_out1(13);
  Selector_out1(39) <= Convert_1_D_to_2_D_out1(15);
  Selector_out1(40) <= Convert_1_D_to_2_D_out1(17);
  Selector_out1(41) <= Convert_1_D_to_2_D_out1(19);
  Selector_out1(42) <= Convert_1_D_to_2_D_out1(21);
  Selector_out1(43) <= Convert_1_D_to_2_D_out1(23);
  Selector_out1(44) <= Convert_1_D_to_2_D_out1(25);
  Selector_out1(45) <= Convert_1_D_to_2_D_out1(27);
  Selector_out1(46) <= Convert_1_D_to_2_D_out1(29);
  Selector_out1(47) <= Convert_1_D_to_2_D_out1(31);
  Selector_out1(48) <= Convert_1_D_to_2_D_out1(33);
  Selector_out1(49) <= Convert_1_D_to_2_D_out1(35);
  Selector_out1(50) <= Convert_1_D_to_2_D_out1(37);
  Selector_out1(51) <= Convert_1_D_to_2_D_out1(39);
  Selector_out1(52) <= Convert_1_D_to_2_D_out1(41);
  Selector_out1(53) <= Convert_1_D_to_2_D_out1(43);
  Selector_out1(54) <= Convert_1_D_to_2_D_out1(45);
  Selector_out1(55) <= Convert_1_D_to_2_D_out1(47);
  Selector_out1(56) <= Convert_1_D_to_2_D_out1(49);
  Selector_out1(57) <= Convert_1_D_to_2_D_out1(51);
  Selector_out1(58) <= Convert_1_D_to_2_D_out1(53);
  Selector_out1(59) <= Convert_1_D_to_2_D_out1(55);
  Selector_out1(60) <= Convert_1_D_to_2_D_out1(57);
  Selector_out1(61) <= Convert_1_D_to_2_D_out1(59);
  Selector_out1(62) <= Convert_1_D_to_2_D_out1(61);
  Selector_out1(63) <= Convert_1_D_to_2_D_out1(63);



  Reshape_out1_gen:FOR k IN 0 TO 63 GENERATE
    Reshape_out1(k) <= Selector_out1(k);
  END GENERATE;


  outputgen: FOR k IN 0 TO 63 GENERATE
    OUT_1(k) <= std_logic_vector(Reshape_out1(k));
  END GENERATE;

END rtl;