viterbi_block_tb.vhd.bak

这是一个计算维特比译码的程序

-- -------------------------------------------------------------
--
-- Module: viterbi_block_tb_pkg
-- Simulink Path: hdlsrc
-- Created: 2009-03-13 14:58:04
-- Description: test bench package
--
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE work.viterbi_block_pkg.ALL;

PACKAGE viterbi_block_tb_pkg IS

  -- Type Definitions
  TYPE GatewayIn_1_type IS ARRAY (0 TO 800) OF vector_of_std_logic_vector6(0 TO 1);
  TYPE Out1_type IS ARRAY (0 TO 800) OF std_logic;

  -- Constants
  CONSTANT GatewayIn_1_force : GatewayIn_1_type;
  CONSTANT Out1_expected : Out1_type;

  -- Functions
  FUNCTION to_integer( x : IN std_logic) RETURN integer;
  FUNCTION to_hex( x : IN std_logic) RETURN string;
  FUNCTION to_hex( x : IN std_logic_vector) RETURN string;
  FUNCTION to_hex( x : IN bit_vector ) RETURN string;
  FUNCTION to_hex( x : IN signed ) RETURN string;
  FUNCTION to_hex( x : IN unsigned ) RETURN string;
  FUNCTION to_hex( x : IN real ) RETURN string;
  FUNCTION to_hex( x : IN vector_of_std_logic_vector6) RETURN string;

  -- Procedures
  PROCEDURE GatewayIn_1_procedure 
    (SIGNAL clk      : IN    std_logic;
     SIGNAL reset    : IN    std_logic;
     SIGNAL rdenb    : IN    std_logic;
     SIGNAL addr     : INOUT unsigned(9 DOWNTO 0);
     SIGNAL nxt_addr : INOUT unsigned(9 DOWNTO 0);
     SIGNAL done     : OUT   std_logic);

  PROCEDURE Out1_procedure 
    (SIGNAL clk      : IN    std_logic;
     SIGNAL reset    : IN    std_logic;
     SIGNAL rdenb    : IN    std_logic;
     SIGNAL addr     : INOUT unsigned(9 DOWNTO 0);
     SIGNAL nxt_addr : INOUT unsigned(9 DOWNTO 0);
     SIGNAL done     : OUT   std_logic);

END viterbi_block_tb_pkg;

PACKAGE BODY viterbi_block_tb_pkg IS
  FUNCTION to_integer( x : IN std_logic) RETURN integer IS
    VARIABLE int: integer;
  BEGIN
    IF x = '0' THEN
      int := 0;
    ELSE
      int := 1;
    END IF;
    RETURN int;
  END;

  FUNCTION to_hex( x : IN std_logic_vector) RETURN string IS
    VARIABLE result  : STRING(1 TO 256); -- 1024 bits max
    VARIABLE i       : INTEGER;
    VARIABLE imod    : INTEGER;
    VARIABLE j       : INTEGER;
    VARIABLE newx    : std_logic_vector(1023 DOWNTO 0);
  BEGIN
    newx := (OTHERS => '0');
    newx(x'RANGE) := x;
    i := x'LENGTH-1;
    imod := x'LENGTH MOD 4;
    IF    imod = 1 THEN i := i+3;
    ELSIF imod = 2 THEN i := i+2;
    ELSIF imod = 3 THEN i := i+1;
    END IF;
    j := 1;
    WHILE i >= 3 LOOP
      IF    newx(i DOWNTO (i-3)) = "0000" THEN result(j) := '0';
      ELSIF newx(i DOWNTO (i-3)) = "0001" THEN result(j) := '1';
      ELSIF newx(i DOWNTO (i-3)) = "0010" THEN result(j) := '2';
      ELSIF newx(i DOWNTO (i-3)) = "0011" THEN result(j) := '3';
      ELSIF newx(i DOWNTO (i-3)) = "0100" THEN result(j) := '4';
      ELSIF newx(i DOWNTO (i-3)) = "0101" THEN result(j) := '5';
      ELSIF newx(i DOWNTO (i-3)) = "0110" THEN result(j) := '6';
      ELSIF newx(i DOWNTO (i-3)) = "0111" THEN result(j) := '7';
      ELSIF newx(i DOWNTO (i-3)) = "1000" THEN result(j) := '8';
      ELSIF newx(i DOWNTO (i-3)) = "1001" THEN result(j) := '9';
      ELSIF newx(i DOWNTO (i-3)) = "1010" THEN result(j) := 'A';
      ELSIF newx(i DOWNTO (i-3)) = "1011" THEN result(j) := 'B';
      ELSIF newx(i DOWNTO (i-3)) = "1100" THEN result(j) := 'C';
      ELSIF newx(i DOWNTO (i-3)) = "1101" THEN result(j) := 'D';
      ELSIF newx(i DOWNTO (i-3)) = "1110" THEN result(j) := 'E';
      ELSIF newx(i DOWNTO (i-3)) = "1111" THEN result(j) := 'F';
      ELSE result(j) := 'X';
      END IF;
      i := i-4;
      j := j+1;
    END LOOP;
    RETURN result(1 TO j-1);
  END;


  FUNCTION to_hex( x : IN std_logic ) RETURN string IS
  BEGIN
    RETURN std_logic'image(x);
  END;


  FUNCTION to_hex( x : IN bit_vector ) RETURN string IS
  BEGIN
    RETURN to_hex( to_stdlogicvector(x) );
  END;


  FUNCTION to_hex( x : IN signed ) RETURN string IS
  BEGIN
    RETURN to_hex( std_logic_vector(x) );
  END;


  FUNCTION to_hex( x : IN unsigned ) RETURN string IS
  BEGIN
    RETURN to_hex( std_logic_vector(x) );
  END;


  FUNCTION to_hex( x : IN real ) RETURN string IS
  BEGIN
    RETURN real'image(x);
  END;


  FUNCTION to_hex( x : IN vector_of_std_logic_vector6) RETURN string IS
    VARIABLE result  : STRING(1 TO 256); -- 1024 bits max
    VARIABLE i       : INTEGER;
    VARIABLE j       : INTEGER;
    VARIABLE k       : INTEGER;
    VARIABLE m       : INTEGER;
    VARIABLE newx    : STRING(1 to 32);
  BEGIN
    i := x'LENGTH-1;
    m := to_hex(x(0))'LENGTH;
    newx(1 to m) := to_hex(x(0));
    k := m;
    result(1 to m) := newx(1 to m);
    for j in 1 to i loop
      result(k+1) := ' ';
      k := k+1;
      newx(1 to m) := to_hex(x(j));
      result(k+1 to k+m) := newx(1 to m);
      k := k+m;
    end loop;
    RETURN result(1 TO k);
  END;

  PROCEDURE GatewayIn_1_procedure 
    (SIGNAL clk      : IN    std_logic;
     SIGNAL reset    : IN    std_logic;
     SIGNAL rdenb    : IN    std_logic;
     SIGNAL addr     : INOUT unsigned(9 DOWNTO 0);
     SIGNAL nxt_addr : INOUT unsigned(9 DOWNTO 0);
     SIGNAL done     : OUT   std_logic) IS
  BEGIN
-- Counter to generate Addr.
    IF reset  = '1' THEN
      addr     <= TO_UNSIGNED(0,10);
    ELSIF clk'event and clk = '1' THEN
      IF rdenb = '1' THEN
        IF (addr = TO_UNSIGNED(800, 10 )) THEN
          addr     <= addr; 
        ELSE
          addr     <= addr + TO_UNSIGNED(1,10); 
        END IF;
      ELSE 
        addr <= addr;
      END IF;
    END IF;

-- Next Address to get reference data in advance.
    IF reset  = '1' THEN
      nxt_addr <= TO_UNSIGNED(0,10);
    ELSIF (nxt_addr < TO_UNSIGNED(800, 10 )) THEN
      nxt_addr <= addr + TO_UNSIGNED(1,10); 
    END IF;

-- Done Signal generation.
    IF reset  = '1' THEN
      done <= '0'; 
    ELSIF (addr = TO_UNSIGNED(800, 10 )) THEN
      done <= '1'; 
    ELSE
      done <= '0'; 
    END IF;
  END GatewayIn_1_procedure;

  PROCEDURE Out1_procedure 
    (SIGNAL clk      : IN    std_logic;
     SIGNAL reset    : IN    std_logic;
     SIGNAL rdenb    : IN    std_logic;
     SIGNAL addr     : INOUT unsigned(9 DOWNTO 0);
     SIGNAL nxt_addr : INOUT unsigned(9 DOWNTO 0);
     SIGNAL done     : OUT   std_logic) IS
  BEGIN
-- Counter to generate Addr.
    IF reset  = '1' THEN
      addr     <= TO_UNSIGNED(0,10);
    ELSIF clk'event and clk = '1' THEN
      IF rdenb = '1' THEN
        IF (addr = TO_UNSIGNED(800, 10 )) THEN
          addr     <= addr; 
        ELSE
          addr     <= addr + TO_UNSIGNED(1,10); 
        END IF;
      ELSE 
        addr <= addr;
      END IF;
    END IF;

-- Next Address to get reference data in advance.
    IF reset  = '1' THEN
      nxt_addr <= TO_UNSIGNED(0,10);
    ELSIF (nxt_addr < TO_UNSIGNED(800, 10 )) THEN
      nxt_addr <= addr + TO_UNSIGNED(1,10); 
    END IF;

-- Done Signal generation.
    IF reset  = '1' THEN
      done <= '0'; 
    ELSIF (addr = TO_UNSIGNED(800, 10 )) THEN
      done <= '1'; 
    ELSE
      done <= '0'; 
    END IF;
  END Out1_procedure;

  CONSTANT GatewayIn_1_force : GatewayIn_1_type :=
    (
      (
        to_stdlogicvector(bit_vector'(X"3a"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"39"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"32"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"04"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"38"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"01"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"3e"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"3f"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"3f"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"3e"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"09"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"12"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"3c"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"0d"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"29"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"36"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"28"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"08"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"30"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"3f"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"3d"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"36"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"07"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"3f"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"0a"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"3d"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"03"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"3f"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"39"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"36"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"05"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"35"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"12"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"06"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"05"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"14"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"01"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"01"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"3b"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"38"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"02"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"0a"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"03"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"06"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"2c"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"0e"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"39"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"39"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"03"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"3f"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"07"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"0e"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"05"))(5 DOWNTO 0),
        to_stdlogicvector(bit_vector'(X"0f"))(5 DOWNTO 0)),
      (
        to_stdlogicvector(bit_vector'(X"33"))(5 DOWNTO 0),