acs.vhd

这是一个计算维特比译码的程序

  outputgen27: FOR k IN 0 TO 3 GENERATE
    s_6(k) <= std_logic_vector(Demux4_out2(k));
  END GENERATE;

  outputgen26: FOR k IN 0 TO 3 GENERATE
    s_7(k) <= std_logic_vector(Demux4_out3(k));
  END GENERATE;

  outputgen25: FOR k IN 0 TO 3 GENERATE
    s_8(k) <= std_logic_vector(Demux4_out4(k));
  END GENERATE;

  Mux3_out1_1_gen:FOR k IN 0 TO 3 GENERATE
    Mux3_out1(k) <= Subsystem4_out2(k);
  END GENERATE;

  Mux3_out1_2_gen:FOR k IN 0 TO 3 GENERATE
    Mux3_out1(k+4) <= Subsystem5_out2(k);
  END GENERATE;

  Mux3_out1_3_gen:FOR k IN 0 TO 3 GENERATE
    Mux3_out1(k+8) <= Subsystem6_out2(k);
  END GENERATE;

  Mux3_out1_4_gen:FOR k IN 0 TO 3 GENERATE
    Mux3_out1(k+12) <= Subsystem7_out2(k);
  END GENERATE;



  Demux5_out1(0 TO 3) <= Demux2_out3(0 TO 3);

  Demux5_out2(0 TO 3) <= Demux2_out3(4 TO 7);

  Demux5_out3(0 TO 3) <= Demux2_out3(8 TO 11);

  Demux5_out4(0 TO 3) <= Demux2_out3(12 TO 15);



  outputgen24: FOR k IN 0 TO 3 GENERATE
    s_9(k) <= std_logic_vector(Demux5_out1(k));
  END GENERATE;

  outputgen23: FOR k IN 0 TO 3 GENERATE
    s_10(k) <= std_logic_vector(Demux5_out2(k));
  END GENERATE;

  outputgen22: FOR k IN 0 TO 3 GENERATE
    s_11(k) <= std_logic_vector(Demux5_out3(k));
  END GENERATE;

  outputgen21: FOR k IN 0 TO 3 GENERATE
    s_12(k) <= std_logic_vector(Demux5_out4(k));
  END GENERATE;

  Mux5_out1_1_gen:FOR k IN 0 TO 3 GENERATE
    Mux5_out1(k) <= Subsystem8_out2(k);
  END GENERATE;

  Mux5_out1_2_gen:FOR k IN 0 TO 3 GENERATE
    Mux5_out1(k+4) <= Subsystem9_out2(k);
  END GENERATE;

  Mux5_out1_3_gen:FOR k IN 0 TO 3 GENERATE
    Mux5_out1(k+8) <= Subsystem10_out2(k);
  END GENERATE;

  Mux5_out1_4_gen:FOR k IN 0 TO 3 GENERATE
    Mux5_out1(k+12) <= Subsystem11_out2(k);
  END GENERATE;



  Demux6_out1(0 TO 3) <= Demux2_out4(0 TO 3);

  Demux6_out2(0 TO 3) <= Demux2_out4(4 TO 7);

  Demux6_out3(0 TO 3) <= Demux2_out4(8 TO 11);

  Demux6_out4(0 TO 3) <= Demux2_out4(12 TO 15);



  outputgen20: FOR k IN 0 TO 3 GENERATE
    s_13(k) <= std_logic_vector(Demux6_out1(k));
  END GENERATE;

  outputgen19: FOR k IN 0 TO 3 GENERATE
    s_14(k) <= std_logic_vector(Demux6_out2(k));
  END GENERATE;

  outputgen18: FOR k IN 0 TO 3 GENERATE
    s_15(k) <= std_logic_vector(Demux6_out3(k));
  END GENERATE;

  outputgen17: FOR k IN 0 TO 3 GENERATE
    s_16(k) <= std_logic_vector(Demux6_out4(k));
  END GENERATE;

  Mux7_out1_1_gen:FOR k IN 0 TO 3 GENERATE
    Mux7_out1(k) <= Subsystem12_out2(k);
  END GENERATE;

  Mux7_out1_2_gen:FOR k IN 0 TO 3 GENERATE
    Mux7_out1(k+4) <= Subsystem13_out2(k);
  END GENERATE;

  Mux7_out1_3_gen:FOR k IN 0 TO 3 GENERATE
    Mux7_out1(k+8) <= Subsystem14_out2(k);
  END GENERATE;

  Mux7_out1_4_gen:FOR k IN 0 TO 3 GENERATE
    Mux7_out1(k+12) <= Subsystem15_out2(k);
  END GENERATE;



  Mux9_out1_1_gen:FOR k IN 0 TO 15 GENERATE
    Mux9_out1(k) <= Mux1_out1(k);
  END GENERATE;

  Mux9_out1_2_gen:FOR k IN 0 TO 15 GENERATE
    Mux9_out1(k+16) <= Mux3_out1(k);
  END GENERATE;

  Mux9_out1_3_gen:FOR k IN 0 TO 15 GENERATE
    Mux9_out1(k+32) <= Mux5_out1(k);
  END GENERATE;

  Mux9_out1_4_gen:FOR k IN 0 TO 15 GENERATE
    Mux9_out1(k+48) <= Mux7_out1(k);
  END GENERATE;



  DEC <= Mux9_out1;

  outputgen16: FOR k IN 0 TO 3 GENERATE
    s_17(k) <= Subsystem_out1(k);
  END GENERATE;

  outputgen15: FOR k IN 0 TO 3 GENERATE
    s_18(k) <= Subsystem1_out1(k);
  END GENERATE;

  outputgen14: FOR k IN 0 TO 3 GENERATE
    s_19(k) <= Subsystem2_out1(k);
  END GENERATE;

  outputgen13: FOR k IN 0 TO 3 GENERATE
    s_20(k) <= Subsystem3_out1(k);
  END GENERATE;

  Mux_out1_1_gen:FOR k IN 0 TO 3 GENERATE
    Mux_out1(k) <= s_17(k);
  END GENERATE;

  Mux_out1_2_gen:FOR k IN 0 TO 3 GENERATE
    Mux_out1(k+4) <= s_18(k);
  END GENERATE;

  Mux_out1_3_gen:FOR k IN 0 TO 3 GENERATE
    Mux_out1(k+8) <= s_19(k);
  END GENERATE;

  Mux_out1_4_gen:FOR k IN 0 TO 3 GENERATE
    Mux_out1(k+12) <= s_20(k);
  END GENERATE;



  outputgen12: FOR k IN 0 TO 3 GENERATE
    s_21(k) <= Subsystem4_out1(k);
  END GENERATE;

  outputgen11: FOR k IN 0 TO 3 GENERATE
    s_22(k) <= Subsystem5_out1(k);
  END GENERATE;

  outputgen10: FOR k IN 0 TO 3 GENERATE
    s_23(k) <= Subsystem6_out1(k);
  END GENERATE;

  outputgen9: FOR k IN 0 TO 3 GENERATE
    s_24(k) <= Subsystem7_out1(k);
  END GENERATE;

  Mux2_out1_1_gen:FOR k IN 0 TO 3 GENERATE
    Mux2_out1(k) <= s_21(k);
  END GENERATE;

  Mux2_out1_2_gen:FOR k IN 0 TO 3 GENERATE
    Mux2_out1(k+4) <= s_22(k);
  END GENERATE;

  Mux2_out1_3_gen:FOR k IN 0 TO 3 GENERATE
    Mux2_out1(k+8) <= s_23(k);
  END GENERATE;

  Mux2_out1_4_gen:FOR k IN 0 TO 3 GENERATE
    Mux2_out1(k+12) <= s_24(k);
  END GENERATE;



  outputgen8: FOR k IN 0 TO 3 GENERATE
    s_25(k) <= Subsystem8_out1(k);
  END GENERATE;

  outputgen7: FOR k IN 0 TO 3 GENERATE
    s_26(k) <= Subsystem9_out1(k);
  END GENERATE;

  outputgen6: FOR k IN 0 TO 3 GENERATE
    s_27(k) <= Subsystem10_out1(k);
  END GENERATE;

  outputgen5: FOR k IN 0 TO 3 GENERATE
    s_28(k) <= Subsystem11_out1(k);
  END GENERATE;

  Mux4_out1_1_gen:FOR k IN 0 TO 3 GENERATE
    Mux4_out1(k) <= s_25(k);
  END GENERATE;

  Mux4_out1_2_gen:FOR k IN 0 TO 3 GENERATE
    Mux4_out1(k+4) <= s_26(k);
  END GENERATE;

  Mux4_out1_3_gen:FOR k IN 0 TO 3 GENERATE
    Mux4_out1(k+8) <= s_27(k);
  END GENERATE;

  Mux4_out1_4_gen:FOR k IN 0 TO 3 GENERATE
    Mux4_out1(k+12) <= s_28(k);
  END GENERATE;



  outputgen4: FOR k IN 0 TO 3 GENERATE
    s_29(k) <= Subsystem12_out1(k);
  END GENERATE;

  outputgen3: FOR k IN 0 TO 3 GENERATE
    s_30(k) <= Subsystem13_out1(k);
  END GENERATE;

  outputgen2: FOR k IN 0 TO 3 GENERATE
    s_31(k) <= Subsystem14_out1(k);
  END GENERATE;

  outputgen1: FOR k IN 0 TO 3 GENERATE
    s_32(k) <= Subsystem15_out1(k);
  END GENERATE;

  Mux6_out1_1_gen:FOR k IN 0 TO 3 GENERATE
    Mux6_out1(k) <= s_29(k);
  END GENERATE;

  Mux6_out1_2_gen:FOR k IN 0 TO 3 GENERATE
    Mux6_out1(k+4) <= s_30(k);
  END GENERATE;

  Mux6_out1_3_gen:FOR k IN 0 TO 3 GENERATE
    Mux6_out1(k+8) <= s_31(k);
  END GENERATE;

  Mux6_out1_4_gen:FOR k IN 0 TO 3 GENERATE
    Mux6_out1(k+12) <= s_32(k);
  END GENERATE;



  Mux8_out1_1_gen:FOR k IN 0 TO 15 GENERATE
    Mux8_out1(k) <= Mux_out1(k);
  END GENERATE;

  Mux8_out1_2_gen:FOR k IN 0 TO 15 GENERATE
    Mux8_out1(k+16) <= Mux2_out1(k);
  END GENERATE;

  Mux8_out1_3_gen:FOR k IN 0 TO 15 GENERATE
    Mux8_out1(k+32) <= Mux4_out1(k);
  END GENERATE;

  Mux8_out1_4_gen:FOR k IN 0 TO 15 GENERATE
    Mux8_out1(k+48) <= Mux6_out1(k);
  END GENERATE;


--store the new switch measures
  outputgen: FOR k IN 0 TO 63 GENERATE
    NSM(k) <= std_logic_vector(Mux8_out1(k));
  END GENERATE;

END rtl;