acs.vhd

这是一个计算维特比译码的程序

-- -------------------------------------------------------------
--
-- Module: ACS
-- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit/ACS
-- Created: 2009-03-24 16:23:40
-- Hierarchy Level: 2
--BM input the branch measures
--SM Input the switch measures
--DEC decoder
--NSM store the new switch
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.viterbi_block_pkg.ALL;

ENTITY ACS IS
  PORT( clk                               :   IN    std_logic;
        reset                             :   IN    std_logic;
        enb                               :   IN    std_logic;
        BM                                :   IN    vector_of_std_logic_vector4(0 TO 3);  
        SM                                :   IN    vector_of_std_logic_vector4(0 TO 63);  
        DEC                               :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
        NSM                               :   OUT   vector_of_std_logic_vector4(0 TO 63)  
        );
END ACS;


ARCHITECTURE rtl OF ACS IS

  -- Component Declarations
  COMPONENT Subsystem
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 3);  
          DEC                             :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]
          );
  END COMPONENT;

  COMPONENT Subsystem1
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 3); 
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 3);  
          DEC                             :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]
          );
  END COMPONENT;

  COMPONENT Subsystem2
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 3);  
          DEC                             :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]
          );
  END COMPONENT;

  COMPONENT Subsystem3
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 3);  
          DEC                             :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]
          );
  END COMPONENT;

  COMPONENT Subsystem4
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 3);  
          DEC                             :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]
          );
  END COMPONENT;

  COMPONENT Subsystem5
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 3);  
          DEC                             :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]
          );
  END COMPONENT;

  COMPONENT Subsystem6
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 3);  
          DEC                             :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]
          );
  END COMPONENT;

  COMPONENT Subsystem7
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 3);  
          DEC                             :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]
          );
  END COMPONENT;

  COMPONENT Subsystem8
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 3); 
          DEC                             :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]
          );
  END COMPONENT;

  COMPONENT Subsystem9
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 3);  
          DEC                             :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]
          );
  END COMPONENT;

  COMPONENT Subsystem10
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3); 
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 3);  
          DEC                             :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]
          );
  END COMPONENT;

  COMPONENT Subsystem11
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 3);  
          DEC                             :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]
          );
  END COMPONENT;

  COMPONENT Subsystem12
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 3);  
          DEC                             :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]
          );
  END COMPONENT;

  COMPONENT Subsystem13
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 3);  
          DEC                             :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]
          );
  END COMPONENT;

  COMPONENT Subsystem14
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 3);  
          DEC                             :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]
          );
  END COMPONENT;

  COMPONENT Subsystem15
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3);  
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 3);  
          DEC                             :   OUT   std_logic_vector(0 TO 3)  -- boolean [4]
          );
  END COMPONENT;

  -- Component Configuration Statements
  FOR ALL : Subsystem
    USE ENTITY work.Subsystem(rtl);

  FOR ALL : Subsystem1
    USE ENTITY work.Subsystem1(rtl);

  FOR ALL : Subsystem2
    USE ENTITY work.Subsystem2(rtl);

  FOR ALL : Subsystem3
    USE ENTITY work.Subsystem3(rtl);

  FOR ALL : Subsystem4
    USE ENTITY work.Subsystem4(rtl);

  FOR ALL : Subsystem5
    USE ENTITY work.Subsystem5(rtl);

  FOR ALL : Subsystem6
    USE ENTITY work.Subsystem6(rtl);

  FOR ALL : Subsystem7
    USE ENTITY work.Subsystem7(rtl);

  FOR ALL : Subsystem8
    USE ENTITY work.Subsystem8(rtl);

  FOR ALL : Subsystem9
    USE ENTITY work.Subsystem9(rtl);

  FOR ALL : Subsystem10
    USE ENTITY work.Subsystem10(rtl);

  FOR ALL : Subsystem11
    USE ENTITY work.Subsystem11(rtl);

  FOR ALL : Subsystem12
    USE ENTITY work.Subsystem12(rtl);

  FOR ALL : Subsystem13
    USE ENTITY work.Subsystem13(rtl);

  FOR ALL : Subsystem14
    USE ENTITY work.Subsystem14(rtl);

  FOR ALL : Subsystem15
    USE ENTITY work.Subsystem15(rtl);

  -- Local Type Definitions
  TYPE vector_of_unsigned4 IS ARRAY (NATURAL RANGE <>) OF std_logic_vector(3 DOWNTO 0);

  -- Signals
  SIGNAL s                                : vector_of_unsigned4(0 TO 63);  
  SIGNAL Demux2_out1                      : vector_of_unsigned4(0 TO 15);  
  SIGNAL Demux2_out2                      : vector_of_unsigned4(0 TO 15);  
  SIGNAL Demux2_out3                      : vector_of_unsigned4(0 TO 15);  
  SIGNAL Demux2_out4                      : vector_of_unsigned4(0 TO 15);  
  SIGNAL Demux1_out1                      : vector_of_unsigned4(0 TO 3);  
  SIGNAL Demux1_out2                      : vector_of_unsigned4(0 TO 3);  
  SIGNAL Demux1_out3                      : vector_of_unsigned4(0 TO 3);  
  SIGNAL Demux1_out4                      : vector_of_unsigned4(0 TO 3);  
  SIGNAL s_1                              : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem_out1                   : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem_out2                   : std_logic_vector(0 TO 3);  -- boolean [4]
  SIGNAL s_2                              : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem1_out1                  : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem1_out2                  : std_logic_vector(0 TO 3);  -- boolean [4]
  SIGNAL s_3                              : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem2_out1                  : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem2_out2                  : std_logic_vector(0 TO 3);  -- boolean [4]
  SIGNAL s_4                              : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem3_out1                  : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem3_out2                  : std_logic_vector(0 TO 3);  -- boolean [4]
  SIGNAL Mux1_out1                        : std_logic_vector(0 TO 15);  -- boolean [16]
  SIGNAL Demux4_out1                      : vector_of_unsigned4(0 TO 3);  
  SIGNAL Demux4_out2                      : vector_of_unsigned4(0 TO 3);  
  SIGNAL Demux4_out3                      : vector_of_unsigned4(0 TO 3);  
  SIGNAL Demux4_out4                      : vector_of_unsigned4(0 TO 3);  
  SIGNAL s_5                              : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem4_out1                  : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem4_out2                  : std_logic_vector(0 TO 3);  -- boolean [4]
  SIGNAL s_6                              : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem5_out1                  : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem5_out2                  : std_logic_vector(0 TO 3);  -- boolean [4]
  SIGNAL s_7                              : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem6_out1                  : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem6_out2                  : std_logic_vector(0 TO 3);  -- boolean [4]
  SIGNAL s_8                              : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem7_out1                  : vector_of_std_logic_vector4(0 TO 3);  
  SIGNAL Subsystem7_out2                  : std_logic_vector(0 TO 3);  -- boolean [4]
  SIGNAL Mux3_out1                        : std_logic_vector(0 TO 15);  -- boolean [16]
  SIGNAL Demux5_out1                      : vector_of_unsigned4(0 TO 3);  
  SIGNAL Demux5_out2                      : vector_of_unsigned4(0 TO 3);