ccd_pkg.vhd

将VHDL源文件中提取常量转换成C/C++的头文件。用于VHDL的固件和主机程序间的同步

library ieee;
use ieee.std_logic_1164.all;
--use IEEE.numeric_bit.all;
--use ieee.numeric_std.all;
use ieee.std_logic_arith.all;

use work.wishbone.all;

package ccd is

	constant CCD_PORT_BITS			: integer := 2;
	constant CCD_PORT_NUM			: integer := 2 ** CCD_PORT_BITS;
    constant CCD_FRAME_BITS			: integer := 8;
    constant CCD_LINE_BITS			: integer := 4;    

	constant CCD_PIX_DEPTH : integer := 16;
	subtype ccd_pix_data is std_logic_vector(CCD_PIX_DEPTH-1 downto 0);

	component virtual_ccd
    
--    generic (
--		VCCD_BADDR_BITS			: integer := 14; -- 16k
--		VCCD_PADDR_BITS			: integer := CCD_FRAME_BITS - CCD_PORT_BITS
--    );
        
    port (

	   -- WB slave IF

        wb_rst_i                : in std_logic;   
        wb_clk_i                : in std_logic;   
        					 
        wb_adr_i              	: in wishbone_addr;   
        wb_dat_i              	: in wishbone_data;   
        wb_dat_o              	: out wishbone_data;   
        wb_we_i               	: in std_logic;   
        wb_stb_i              	: in std_logic;   
        wb_ack_o              	: out std_logic;   
        wb_cyc_i              	: in std_logic;   
        
		-- CCD signal port
		
		ccd_sof_o				: out std_logic;
		ccd_sol_o				: out std_logic;
		ccd_pen_o				: out std_logic;
		ccd_port0_o				: out ccd_pix_data;
		ccd_port1_o				: out ccd_pix_data;
		ccd_port2_o				: out ccd_pix_data;
		ccd_port3_o				: out ccd_pix_data
		
--		clk_i					: in std_logic
		
	);   

	end component;

	component ccd_interface is
    
--    generic (
--		CCDIF_BADDR_BITS			: integer := 14; -- 16k
--		CCDIF_PADDR_BITS			: integer := CCD_FRAME_BITS - CCD_PORT_BITS
--   );
        
    port (

	   -- WB slave IF

        wb_rst_i                : in std_logic;   
        wb_clk_i                : in std_logic;   
        					 
        wb_adr_i              	: in wishbone_addr;   
        wb_dat_i              	: in wishbone_data;   
        wb_dat_o              	: out wishbone_data;   
        wb_we_i               	: in std_logic;   
        wb_stb_i              	: in std_logic;   
        wb_ack_o              	: out std_logic;   
        wb_cyc_i              	: in std_logic;   
        
		-- CCD signal input ports
		
		ccd_sof_i				: in std_logic := '0';
		ccd_sol_i				: in std_logic := '0';
		ccd_pen_i				: in std_logic := '0';
		ccd_port0_i				: in ccd_pix_data := (others => '0');
		ccd_port1_i				: in ccd_pix_data := (others => '0');
		ccd_port2_i				: in ccd_pix_data := (others => '0');
		ccd_port3_i				: in ccd_pix_data := (others => '0');
		
		-- CCD signal output ports
		
		ccd_sof_o				: out std_logic;
		ccd_sol_o				: out std_logic;
		ccd_pen_o				: out std_logic;
		ccd_port0_o				: out ccd_pix_data;
		ccd_port1_o				: out ccd_pix_data;
		ccd_port2_o				: out ccd_pix_data;
		ccd_port3_o				: out ccd_pix_data
		
	);   

	end component;

    function ccd_info(  -- 32 bit in total
    	ports 			: in integer;
    	sizex			: in integer;
    	sizey			: in integer;
    	color_depth		: in integer;
    	bypass 			: in std_logic;
    	virtual 		: in std_logic;
    	grabber 		: in std_logic
    ) return wishbone_data;
    
end ccd;

package body ccd is

    function ccd_info(  -- 32 bit in total
    	ports 			: in integer;
    	sizex			: in integer;
    	sizey			: in integer;
    	color_depth		: in integer;
    	bypass 			: in std_logic;
    	virtual 		: in std_logic;
    	grabber 		: in std_logic
    ) return wishbone_data is
    	variable info : wishbone_data := (others => '0');
    	
    	alias info_ports : std_logic_vector( WISHBONE_INF_CCD_PORTS_LEN - 1 downto 0) is
    		info( WISHBONE_INF_CCD_PORTS_BIT + WISHBONE_INF_CCD_PORTS_LEN - 1 downto WISHBONE_INF_CCD_PORTS_BIT);
    	
    	alias info_sizex4 : std_logic_vector( WISHBONE_INF_CCD_SIZEX4_LEN - 1 downto 0) is
    		info( WISHBONE_INF_CCD_SIZEX4_BIT + WISHBONE_INF_CCD_SIZEX4_LEN - 1 downto WISHBONE_INF_CCD_SIZEX4_BIT);
    	
    	alias info_sizey4 : std_logic_vector( WISHBONE_INF_CCD_SIZEY4_LEN - 1 downto 0) is
    		info( WISHBONE_INF_CCD_SIZEY4_BIT + WISHBONE_INF_CCD_SIZEY4_LEN - 1 downto WISHBONE_INF_CCD_SIZEY4_BIT);
    	
    	alias info_depth : std_logic_vector( WISHBONE_INF_CCD_DEPTH_LEN - 1 downto 0) is
    		info( WISHBONE_INF_CCD_DEPTH_BIT + WISHBONE_INF_CCD_DEPTH_LEN - 1 downto WISHBONE_INF_CCD_DEPTH_BIT);
    	
    begin
    	assert (ports < (2 ** WISHBONE_INF_CCD_PORTS_LEN)) report "ccd_info() 'ports' value overflow" severity error;
    	assert ((sizex/4) < (2 ** WISHBONE_INF_CCD_SIZEX4_LEN)) report "ccd_info() 'sizex' value overflow" severity error;
    	assert ((sizey/4) < (2 ** WISHBONE_INF_CCD_SIZEY4_LEN)) report "ccd_info() 'sizey' value overflow" severity error;
    	assert (color_depth < (2 ** WISHBONE_INF_CCD_DEPTH_LEN)) report "ccd_info() 'color_depth' value overflow" severity error;
    	
    	info_ports := conv_std_logic_vector( ports, info_ports'length);
    	info_sizex4 := conv_std_logic_vector( sizex / 4, info_sizex4'length);
    	info_sizey4 := conv_std_logic_vector( sizey / 4, info_sizey4'length);
    	info_depth := conv_std_logic_vector( color_depth, info_depth'length);
    	
    	info(WISHBONE_INF_CCD_BYPASS) := bypass;
    	info(WISHBONE_INF_CCD_VIRTUAL) := virtual;
    	info(WISHBONE_INF_CCD_GRABBER) := grabber;
    	
    	return info;
    end ccd_info;
    

end ccd;

-- EOF