spi.h

f330与mfrc522 通信 构成读卡器 上传源码和原理图。

//*********************************************************
// 项  目:  通用控制器－V1.0
// 文件名: 	Spi.h
// 描  述:  头文件
//*********************************************************
//#ifndef _BYTE_DEF_
//#define _BYTE_DEF_
//typedef unsigned char BYTE;
//#endif   /* _BYTE_DEF_ */
//*********************************************************
//nRF24L01commands
#define READ_REG        0x00  //read command to register
#define WRITE_REG       0x20  //write command to register
#define RD_RX_PLOAD     0x61  //read RX payload register
#define WR_TX_PLOAD     0xA0  //write TX payload register
#define FLUSH_TX        0xE1  //clear flush TX register
#define FLUSH_RX        0xE2  //clear flush RX register
#define REUSE_TX_PL     0xE3  //reuse TX payload register
#define NOP             0xFF  //No Operation/read status register
//***************************************************//
//nRF24L01 registers addresses
#define CONFIG          0x00  // 'Config'
#define EN_AA           0x01  // 'Enable Auto Ack'
#define EN_RXADDR       0x02  // 'Enabled RX '
#define SETUP_AW        0x03  // 'Setup address width' 
#define SETUP_RETR      0x04  // 'Setup Auto. '
#define RF_CH           0x05  // 'RF channel' 
#define RF_SETUP        0x06  // 'RF setup' 
#define STATUS          0x07  // 'Status' 
#define OBSERVE_TX      0x08  // 'Observe TX' 
#define CD              0x09  // 'Carrier Detect' 
#define RX_ADDR_P0      0x0A  // 'RX address pipe0' 
#define RX_ADDR_P1      0x0B  // 'RX address pipe1' 
#define RX_ADDR_P2      0x0C  // 'RX address pipe2' 
#define RX_ADDR_P3      0x0D  // 'RX address pipe3' 
#define RX_ADDR_P4      0x0E  // 'RX address pipe4' 
#define RX_ADDR_P5      0x0F  // 'RX address pipe5' 
#define TX_ADDR         0x10  // 'TX address' 
#define RX_PW_P0        0x11  // 'RX payload width, pipe0' 
#define RX_PW_P1        0x12  // 'RX payload width, pipe1' 
#define RX_PW_P2        0x13  // 'RX payload width, pipe2' 
#define RX_PW_P3        0x14  // 'RX payload width, pipe3'
#define RX_PW_P4        0x15  // 'RX payload width, pipe4' 
#define RX_PW_P5        0x16  // 'RX payload width, pipe5' 
#define FIFO_STATUS     0x17  // 'FIFO Status Register'

#define TX_LENTH        0x10
//===============================================常数定义
#define TX_ADR_WIDTH    5   // 5 bytes TX(RX) address width
#define TX_PLOAD_WIDTH  20  // 20 bytes TX payload
//===============================================函数申明
void Init_Spi(void);
void Init_Ptr6(void);
void Read_All_Reg(void);
void Tst_Ptr6(void);  //

void RX_Mode(void);
void TX_Mode(void);
UCHAR SPI_RW(UCHAR byte);
UCHAR SPI_Read(UCHAR reg);
UCHAR SPI_RW_Reg(UCHAR reg,UCHAR value);
UCHAR SPI_Read_Buf(UCHAR reg,UCHAR *pBuf,UCHAR bytes);
UCHAR SPI_Write_Buf(UCHAR reg, UCHAR *pBuf, UCHAR bytes);
//--------------------------------------------------