brick.vhd

来自「使用FPGA开发的小球挡板游戏 用vga视频接口输出」· VHDL 代码 · 共 44 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity brick is
    Port ( clk : in std_logic;
           reset : in std_logic;
           hcnt : in integer ;
           vcnt : in integer ;
           brick_rgb : out std_logic_vector(2 downto 0));
end brick;

architecture Behavioral of brick is

--------------------------------------------------------------------
CONSTANT BRICK_WIDTH : INTEGER :=40;
CONSTANT BRICK_LEN : INTEGER :=50;
CONSTANT BRICK_AX: INTEGER :=130;
CONSTANT BRICK_BX: INTEGER :=320;
CONSTANT BRICK_CX: INTEGER :=510;
CONSTANT BRICK_Y : INTEGER :=100;
---------------------------------------------------------------------


begin

drawmount: process(clk,hcnt,vcnt,reset)
begin
  if (reset='0') then
      brick_rgb <= "000";
  elsif (clk'event and clk='1') then		
		if ((hcnt>=BRICK_AX- BRICK_LEN and hcnt<=BRICK_AX- BRICK_LEN) and (vcnt>=BRICK_Y - BRICK_WIDTH and vcnt<=BRICK_Y + BRICK_WIDTH))
                  or ((hcnt>=BRICK_BX- BRICK_LEN and hcnt<=BRICK_BX- BRICK_LEN) and (vcnt>=BRICK_Y - BRICK_WIDTH and vcnt<=BRICK_Y + BRICK_WIDTH))                  or ((hcnt>=BRICK_CX- BRICK_LEN and hcnt<=BRICK_CX- BRICK_LEN) and (vcnt>=BRICK_Y - BRICK_WIDTH and vcnt<=BRICK_Y + BRICK_WIDTH))  
                then
	 	  brick_rgb <= "001";
		else
		  brick_rgb <= "000";
		end if;
 end if;
end process;

end Behavioral;