ballgame.vhd

使用FPGA开发的小球挡板游戏 用vga视频接口输出

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ballgame is
    Port (  clk_0 : in std_logic;
            reset,start : in std_logic;
            key_l,key_r : in std_logic;
            hs,vs: buffer std_logic;  
            rgb: buffer std_logic_vector(2 downto 0));
end ballgame;


architecture behav of ballgame is

--------------------------------------------------------------------------------
    constant h_pixels:integer:=640;
    constant h_front:integer:=16;
    constant h_back:integer:=48;
    constant h_synctime:integer:=96;
    constant h_period:integer:=h_synctime+h_pixels+h_front+h_back; --800
    constant v_lines:integer:=480;
    constant v_front:integer:=10;
    constant v_back:integer:=33;
    constant v_synctime:integer:=2;
    constant v_period:integer:=v_synctime+v_lines+v_front+v_back; --525

    CONSTANT BOARD_X0:INTEGER :=320;
    CONSTANT BOARD_Y0:INTEGER :=400;
    CONSTANT BOARD_WIDTH : INTEGER :=20;
    CONSTANT BOARD_LEN : INTEGER :=50;--THIE IS THE 1/2 LENGTH OF BOARD

    
    CONSTANT BRICK_WIDTH : INTEGER :=40;
    CONSTANT BRICK_LEN : INTEGER :=50;
    CONSTANT BRICK_AX: INTEGER :=130;
    CONSTANT BRICK_BX: INTEGER :=320;
    CONSTANT BRICK_CX: INTEGER :=510;
    CONSTANT BRICK_Y : INTEGER :=100;
   
    CONSTANT BALL_R : INTEGER :=5;
--------------------------------------------------------------------------------
signal movclk,clk : std_logic;
signal ball_rgb,board_rgb,brick_rgb :std_logic_vector(2 downto 0);
signal ball_x,ball_y,board_x:  integer;
signal hcnt,vcnt : integer;
---------------------------------------------------------------------------------     
component ball
    Port ( clk : in std_logic;
           reset,start : in std_logic;
	       hcnt : in integer;
           vcnt : in integer;        
           ball_x : buffer integer;
           ball_y : buffer integer;       
           ball_rgb: out std_logic_vector(2 downto 0);
           board_x : buffer integer );
end component;

component brick
    Port ( clk : in std_logic;
           reset : in std_logic;
           hcnt : in integer ;
           vcnt : in integer;
           brick_rgb : out std_logic_vector(2 downto 0));
end component;

component board
    Port ( clk : in std_logic;
           reset : in std_logic;
	       hcnt : in integer ;
           vcnt : in integer;
           board_x : buffer integer;
           board_rgb : out std_logic_vector(2 downto 0));
end component;

component control
    Port ( movclk : in std_logic;
           reset : in std_logic;
           key_l : in std_logic;
           key_r : in std_logic;          
           vcnt : in integer;
           board_x : buffer integer );
end component;

component vga is
    port(clk: in std_logic;reset:in std_logic;
         hs,vs:out std_logic;
         hcnt,vcnt: buffer integer);
end component;




begin
  process (reset,clk_0)
    begin
    if reset ='1' then
       clk<='0';
    elsif clk_0'event and clk_0='1' then 
        clk<=not clk;
    end if;
 end process;
       

 a: ball port map
         ( clk => clk,
           reset => reset,
           start=>start,
           hcnt => hcnt,
           vcnt => vcnt,
           
           ball_x =>ball_x,
           ball_y =>ball_y,     
           ball_rgb =>ball_rgb,
           board_x =>board_x);
  b:brick port map
 	     ( clk =>clk,
           reset => reset,
           hcnt =>hcnt,
           vcnt =>vcnt,
           brick_rgb =>brick_rgb);
  c:board port map
         ( clk=>clk ,
           reset=> reset,
	       hcnt=>hcnt, 
           vcnt=>vcnt,
           board_x=>board_x ,
           board_rgb=>board_rgb );


  d:control port map
         ( movclk=>hs,
           reset=>reset, 
           key_l=>key_l,
           key_r =>key_r ,   
           vcnt =>vcnt,
           board_x=>board_x ) ;


 e: vga port map
        (clk=>clk,
         reset=>reset, 
         hs=>hs,
         vs=>vs,
         hcnt=>hcnt,
         vcnt=>vcnt  ) ;







  rgb <= brick_rgb or board_rgb or ball_rgb;




end behav;