board.vhd

使用FPGA开发的小球挡板游戏 用vga视频接口输出

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity board is
    Port ( clk : in std_logic;
           reset : in std_logic;
	   hcnt : in integer;
           vcnt : in integer;
           board_x : buffer integer;
           board_rgb : out std_logic_vector(2 downto 0));
end board;

architecture Behavioral of board is

---------------------------------------------------------------
CONSTANT BOARD_X0:INTEGER :=320;
CONSTANT BOARD_Y0:INTEGER :=400;
CONSTANT BOARD_WIDTH : INTEGER :=20;
CONSTANT BOARD_LEN : INTEGER :=50;--THIE IS THE 1/2 LENGTH OF BOARD
---------------------------------------------------------------


begin
  drawboard: process(reset,clk,hcnt,vcnt)
  begin
    if reset='0' then
	   board_rgb <= "000";
         
	 elsif (clk'event and clk='1') then
	   if ((hcnt>=board_x - BOARD_LEN) and (hcnt<=board_x+BOARD_LEN)) and ((vcnt>=BOARD_Y0-BOARD_WIDTH) and (vcnt<=BOARD_Y0+BOARD_WIDTH)) then
		   board_rgb <="010";
              else
		   board_rgb <= "000";
           end if; 
     end if;
	end process;
 end Behavioral;