control.vhd

来自「使用FPGA开发的小球挡板游戏 用vga视频接口输出」· VHDL 代码 · 共 41 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity control is
    Port ( movclk : in std_logic;
           reset : in std_logic;
           key_l : in std_logic;
           key_r : in std_logic;          
           vcnt : in integer;
           board_x : buffer integer);
end control;

architecture Behavioral of control is

----------------------------------------------------------------------
CONSTANT BOARD_X0:INTEGER :=320;
CONSTANT BOARD_LEN : INTEGER :=50;--THIE IS THE 1/2 LENGTH OF BOARD
-----------------------------------------------------------------------
begin

boardloc: process(reset,movclk,key_l,key_r)
begin
    if (reset='0') then
        board_x<=BOARD_X0;
    elsif (movclk'event and movclk='1')  then
       
        if key_l='1' and key_r='0' and board_x>=BOARD_LEN  then
             board_x<=board_x-1;
        elsif key_l='0' and key_r='1' and board_x<=640-BOARD_LEN then
             board_x<=board_x+1;
        else
             board_x<=board_x;
        end if;
    end if;
    end process;

end Behavioral;