📄 main.lst
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314 < C_BUZ_Div_2k: EQU %00000110 ; Buzzer:Fto/2^11.
315 < C_BUZ_Div_4k: EQU %00000111 ; Buzzer:Fto/2^12.
316 < C_BUZ_Div_8k: EQU %00001000 ; Buzzer:Fto/2^13.
317 < C_BUZ_Div_4: EQU %00001001 ; Buzzer:Fto/2^2.
318 < C_BUZ_Div_8: EQU %00001010 ; Buzzer:Fto/2^3.
319 < C_BUZ_Div_16: EQU %00001011 ; Buzzer:Fto/2^4.
320 < C_BUZ_Div_32: EQU %00001100 ; Buzzer:Fto/2^5.
321 < ;
322 < ;-----------------------------------------------------------------------------------------------------
323 < ; Double Write Register
324 < P_SYS_Ctrl: EQU $30 ; System control.
325 < C_SCR_POR: EQU %10000000 ; Power On Reset Flag.(A)
326 < C_SCR_ERST: EQU %01000000 ; External Reset Flag.(A)
327 < C_SCR_LVR: EQU %00100000 ; Low Voltage Reset Flag.(A)
328 < C_SCR_WDTR: EQU %00001000 ; WDT Reset Flag.(A)
329 < C_SCR_IAR: EQU %00000100 ; Illegal Address Reset Flag.(A)
330 < C_SCR_IIR: EQU %00000001 ; Illegal instruction reset.(A)
331 <
332 < CB_SCR_POR: EQU 7 ; Power On Reset Flag for bit mode.(A)
333 < CB_SCR_ERST: EQU 6 ; External Reset Flag for bit mode.(A)
334 < CB_SCR_LVR: EQU 5 ; Low Voltage Reset Flag for bit mode.(A)
335 < CB_SCR_WDTR: EQU 3 ; WDT Reset Flag for bit mode.(A)
336 < CB_SCR_IAR: EQU 2 ; Illegal Address Reset Flag for bit mode.(A)
337 < CB_SCR_IIR: EQU 0 ; Illegal instruction reset for bit mode.(A)
338 < ;
339 < P_MODE_Ctrl: EQU $31 ; Operation mode control register.(W)
340 < C_MODE_STOP: EQU $5A ; Enter STOP mode.(W)
341 < C_MODE_HALT: EQU $A5 ; Enter HALT mode.(W)
342 < C_MODE_Reset: EQU $66 ; Reset all of internal modules except CPU.(W)
343 < ;
344 < P_WDT_Ctrl: EQU $32 ; Watchdog control register.
345 < C_WDT_SCKEN: EQU %10000000 ; Slow clock enable bit in stop mode.(A)
346 < ; Selection bits of watchdog interrupt rate.(A)
347 < C_WDT_RTO: EQU %00000000 ; RTO from Timer0 is selected.
348 < C_WDT_Div_256: EQU %00010000 ; WDI clock = /256.
349 < C_WDT_Div_512: EQU %00100000 ; WDI clock = /512.
350 < C_WDT_Div_1024: EQU %00110000 ; WDI clock = /1024.
351 < C_WDT_Div_2048: EQU %01000000 ; WDI clock = /2048.
352 < C_WDT_Div_4096: EQU %01010000 ; WDI clock = /4096.
353 < C_WDT_Div_8192: EQU %01100000 ; WDI clock = /8192.
354 < C_WDT_Div_16384: EQU %01110000 ; WDI clock = /16384.
355 <
356 < CB_WDT_EN: EQU 7 ; Watchdog enable bit in stop mode for bit mode.(A)
357 < ;
358 < P_IRQ_Opt1: EQU $34 ; IRQ Option 1 register.
359 < C_IRQOpt1_IRQ3ES: EQU %10000000 ; Polarity control of INT3.(A)
360 < C_IRQOpt1_IRQM3: EQU %01000000 ; INT3 trigger mode selection.(A)
361 < C_IRQOpt1_IRQ2ES: EQU %00100000 ; Polarity control of INT2.(A)
362 < C_IRQOpt1_IRQM2: EQU %00010000 ; INT2 trigger mode selection.(A)
363 < C_IRQOpt1_IRQ1ES: EQU %00001000 ; Polarity control of INT1.(A)
364 < C_IRQOpt1_IRQM1: EQU %00000100 ; INT1 trigger mode selection.(A)
365 < C_IRQOpt1_IRQ0ES: EQU %00000010 ; Polarity control of INT0.(A)
366 < C_IRQOpt1_IRQM0: EQU %00000001 ; INT0 trigger mode selection.(A)
367 < C_IRQOpt1_CAP3ES: EQU %00001000 ; Polarity control of CAP3.(A)
368 < C_IRQOpt1_CAP2ES: EQU %00000010 ; Polarity control of CAP2.(A)
369 <
370 < CB_IRQOpt1_IRQ3ES: EQU 7 ; Polarity control of INT3 for bit mode.(A)
371 < CB_IRQOpt1_IRQM3: EQU 6 ; INT3 trigger mode selection for bit mode.(A)
372 < CB_IRQOpt1_IRQ2ES: EQU 5 ; Polarity control of INT2 for bit mode.(A)
373 < CB_IRQOpt1_IRQM2: EQU 4 ; INT2 trigger mode selection for bit mode.(A)
374 < CB_IRQOpt1_IRQ1ES: EQU 3 ; Polarity control of INT1 for bit mode.(A)
375 < CB_IRQOpt1_IRQM1: EQU 2 ; INT1 trigger mode selection for bit mode.(A)
376 < CB_IRQOpt1_IRQ0ES: EQU 1 ; Polarity control of INT0 for bit mode.(A)
377 < CB_IRQOpt1_IRQM0: EQU 0 ; INT0 trigger mode selection for bit mode.(A)
378 < CB_IRQOpt1_CAP3ES: EQU 3 ; Polarity control of CAP3 for bit mode.(A)
379 < CB_IRQOpt1_CAP2ES: EQU 1 ; Polarity control of CAP2 for bit mode.(A)
380 < ;
381 < P_IO_Opt: EQU $35 ; I/O slew rate control register.
382 < C_IO_SLOWE: EQU %00000001 ; PB[7:6] slew rate enable selection.(A)
383 <
384 < CB_IO_SLOWE: EQU 0 ; PB[7:6] slew rate enable selection for bit mode.(A)
385 < ;
386 < P_LVR_Opt: EQU $36 ; LVR Option
387 < C_LVR_V40: EQU %00000001 ; LVR level select bit.(A)
388 <
389 < CB_LVR_V40: EQU 0 ; LVR level select bit for bit mode.(A)
390 < ;
391 < ;-----------------------------------------------------------------------------------------------------
392 < P_SPI_Ctrl0: EQU $38 ; SPI control register 0.
393 < C_SPI_EN: EQU %10000000 ; enable Control bit.
394 < C_SPI_MOD: EQU %01000000 ; operation Mode Master/Slave Mode.
395 < C_SPI_SCKPHA: EQU %00100000 ; clock phase.
396 < C_SPI_SCKPOL: EQU %00010000 ; clock polarity.
397 < C_SPI_SPISMPS: EQU %00001000 ; sample mode selection bit for master mode.
398 < C_SPICS_Div_128: EQU %00000101 ; CPU Clock Selection/128.
399 < C_SPICS_Div_64: EQU %00000100 ; CPU Clock Selection/64.
400 < C_SPICS_Div_32: EQU %00000011 ; CPU Clock Selection/32.
401 < C_SPICS_Div_16: EQU %00000010 ; CPU Clock Selection/16.
402 < C_SPICS_Div_8: EQU %00000001 ; CPU Clock Selection/8.
403 < C_SPICS_Div_4: EQU %00000000 ; CPU Clock Selection/4.
404 <
405 < CB_SPI_EN: EQU 7 ; enable Control bit for bit mode.
406 < CB_SPI_MOD: EQU 6 ; operation Mode Master/Slave Mode for bit mode.
407 < CB_SPI_SCKPHA: EQU 5 ; clock phase for bit mode.
408 < CB_SPI_SCKPOL: EQU 4 ; clock polarity for bit mode.
409 < CB_SPI_SPISMPS: EQU 3 ; sample mode selection bit for master mode for bit mode.
410 < ;
411 < P_SPI_Ctrl1: EQU $39 ; SPI control register 1.
412 < C_SPI_SMSEN: EQU %10000000 ; SPI Slave Mode Selection enable bit.
413 < C_SPI_SWRST: EQU %01000000 ; software reset bit.
414 < C_SPISPC_Div_4: EQU %00000011 ; sampling clock Div/4.
415 < C_SPISPC_Div_2: EQU %00000010 ; sampling clock Div/2.
416 < C_SPISPC_Div_1: EQU %00000001 ; sampling clock Div/1.
417 < C_SPISPC_Dis: EQU %00000000 ; no sampling.
418 <
419 < CB_SPI_SMSEN: EQU 7 ; SPI Slave Mode Selection enable bit for bit mode.
420 < CB_SPI_SWRST: EQU 6 ; software reset bit for bit mode.
421 < ;
422 < P_SPI_Status: EQU $3A ; SPI status register
423 < C_SPI_INTIF: EQU %10000000 ; SPI interrupt flag active.
424 < C_SPI_INTEN: EQU %01000000 ; SPI interrupt enable/diable.
425 < C_SPI_TXBF: EQU %00100000 ; transmission buffer full flag.
426 < C_SPI_BUFFull: EQU %00000001 ; buffer full and overwrite.
427 <
428 < CB_SPI_INTIF: EQU 7 ; SPI interrupt flag active for bit mode.
429 < CB_SPI_INTEN: EQU 6 ; SPI interrupt enable/diable for bit mode.
430 < CB_SPI_TXBF: EQU 5 ; transmission buffer full flag for bit mode.
431 < CB_SPI_BUFFull: EQU 0 ; buffer full and overwrite for bit mode.
432 < ;
433 < P_SPI_TxData: EQU $3B ; SPI Transmit data buffer
434 < P_SPI_RxData: EQU $3C ; SPI Receive data buffer
435 < ;
436 < ;-----------------------------------------------------------------------------------------------------
437 < P_CAP_Ctrl: EQU $58 ; Capture control
438 < C_CAP_OPT: EQU %10000000 ; Capture option control bit.(A)
439 < C_CAP_IP3: EQU %00100000 ; CAP3 interrupt evoke polarity.
440 < C_CAP_IP2: EQU %00010000 ; CAP2 interrupt evoke polarity.
441 < C_CAP_IP1: EQU %00001000 ; CAP1 interrupt evoke polarity.
442 < C_CAP_IP0: EQU %00000100 ; CAP0 interrupt evoke polarity.
443 < C_CAP1_ES: EQU %00000010 ; Polarity control of capture1 interrupt.
444 < C_CAP0_ES: EQU %00000001 ; Polarity control of capture0 interrupt.
445 <
446 < CB_CAP_OPT: EQU 7 ; Capture option control bit for bit mode.(A)
447 < CB_CAP_IP3: EQU 5 ; CAP3 interrupt evoke polarity for bit mode.
448 < CB_CAP_IP2: EQU 4 ; CAP2 interrupt evoke polarity for bit mode.
449 < CB_CAP_IP1: EQU 3 ; CAP1 interrupt evoke polarity for bit mode.
450 < CB_CAP_IP0: EQU 2 ; CAP0 interrupt evoke polarity for bit mode.
451 < CB_CAP1_ES: EQU 1 ; Polarity control of capture1 interrupt for bit mode.
452 < CB_CAP0_ES: EQU 0 ; Polarity control of capture0 interrupt for bit mode.
453 < ;
454 < ;-----------------------------------------------------------------------------------------------------
455 < P_IOA_Buf: EQU $59
456 < C_IOA_Buf7: EQU %10000000 ; Output data Latch of PORTA bit7.
457 < C_IOA_Buf6: EQU %01000000 ; Output data Latch of PORTA bit6.
458 < C_IOA_Buf5: EQU %00100000 ; Output data Latch of PORTA bit5.
459 < C_IOA_Buf4: EQU %00010000 ; Output data Latch of PORTA bit4.
460 < C_IOA_Buf3: EQU %00001000 ; Output data Latch of PORTA bit3.
461 < C_IOA_Buf2: EQU %00000100 ; Output data Latch of PORTA bit2.
462 < C_IOA_Buf1: EQU %00000010 ; Output data Latch of PORTA bit1.
463 < C_IOA_Buf0: EQU %00000001 ; Output data Latch of PORTA bit0.
464 < P_IOB_Buf: EQU $5A
465 < C_IOB_Buf7: EQU %10000000 ; Output data Latch of PORTB bit7.
466 < C_IOB_Buf6: EQU %01000000 ; Output data Latch of PORTB bit6.
467 < C_IOB_Buf5: EQU %00100000 ; Output data Latch of PORTB bit5.
468 < C_IOB_Buf4: EQU %00010000 ; Output data Latch of PORTB bit4.
469 < C_IOB_Buf3: EQU %00001000 ; Output data Latch of PORTB bit3.
470 < C_IOB_Buf2: EQU %00000100 ; Output data Latch of PORTB bit2.
471 < C_IOB_Buf1: EQU %00000010 ; Output data Latch of PORTB bit1.
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