📄 alu_64x.asm
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XOR .D2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU52 ;ERROR, if B0 !=0
NOP 5
;checking for instruction MVK using .L unit
;Move a signed constant into a register and sign-extend
MVK .L2 -5, B16 ;B16 = src1
MVK .L2 0xFFFFFFFB, B19 ;B19 = result
CMPEQ .L2 B19, B16, B0 ;B0 = 1
[!B0] B .S1 ERRALU53 ;ERROR, if B0 !=0
NOP 5
;checking for instruction MVK using .S unit
MVK .S2 -5, B16 ;B16 = src1
MVK .S2 0xFFFFFFFB, B19 ;B19 = result
CMPEQ .L2 B19, B16, B0 ;B0 = 1
[!B0] B .S1 ERRALU54 ;ERROR, if B0 !=0
NOP 5
;checking for instruction MVK using .D unit
MVK .D2 -5, B16 ;B16 = src1
MVK .D2 0xFFFFFFFB, B19 ;B19 = result
CMPEQ .L2 B19, B16, B0 ;B0 = 1
[!B0] B .S1 ERRALU55 ;ERROR, if B0 !=0
NOP 5
;checking for instruction AND using .L unit
;Bitwise AND
MVKL .S2 0xF7A1302A, B16 ;B16 = src1
MVKH .S2 0xF7A1302A, B16 ;B16 = src1
MVKL .S2 0x02A02020, B18 ;B18 = src2
MVKH .S2 0x02A02020, B18 ;B18 = src2
MVKL .S2 0x02A02020, B19 ;B19 = result
MVKH .S2 0x02A02020, B19 ;B19 = result
AND .L2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU56 ;ERROR, if B0 !=0
NOP 5
;checking for instruction AND using .S unit
AND .S2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU57 ;ERROR, if B0 !=0
NOP 5
;checking for instruction AND using .D unit
AND .D2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU57 ;ERROR, if B0 !=0
NOP 5
;checking for instruction ADDAD
;Interger addition using doubleword addressing mode
MVKL .S2 0x00001234, B16 ;B16 = src1
MVKH .S2 0x00001234, B16 ;B16 = src1
MVKL .S2 0x00000002, B18 ;B18 = src2
MVKH .S2 0x00000002, B18 ;B18 = src2
MVKL .S2 0x00001244, B19 ;B19 = result
MVKH .S2 0x00001244, B19 ;B19 = result
ADDAD .D2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU61 ;ERROR, if B0 !=0
NOP 5
;checking instruction LDDW and STDW
;Store and Load doubleword from memory with an unsigned constant
;offset or register offset
MVKL .S2 0x40213333, B17 ;B16 = src1
MVKH .S2 0x40213333, B17 ;B16 = src1
MVKL .S2 0x33333333, B16 ;B18 = src2
MVKH .S2 0x33333333, B16 ;B18 = src2
;The address used is in internal memory
MVKL .S2 0x000E0000, B18 ;B18 = memory address
MVKH .S2 0x000E0000, B18 ;B18 = memory address
STDW .D2 B17:B16,*B18++
;clear orignal value out of reg to show change
MVKL .S2 0xFFFFFFFF, B17 ;B16 = src1
MVKH .S2 0xFFFFFFFF, B17 ;B16 = src1
MVKL .S2 0xFFFFFFFF, B16 ;B18 = src2
MVKH .S2 0xFFFFFFFF, B16 ;B18 = src2
LDDW .D2 *-B18[1],B17:B16
MVKL .S2 0x40213333, B24 ;B16 = src1
MVKH .S2 0x40213333, B24 ;B16 = src1
MVKL .S2 0x33333333, B25 ;B18 = src2
MVKH .S2 0x33333333, B25 ;B18 = src2
NOP 1 ;Delay Slot
CMPEQ .L2 B17, B24, B0 ;B0 = 1
[!B0] B .S1 ERRALU62 ;ERROR, if B0 !=0
NOP 5
CMPEQ .L2 B16, B25, B1
[!B1] B .S1 ERRALU63
NOP 5
;checking instruction STNDW and LDNDW
;Store and Load non-aligned double word
MVKL .S2 0x40213333, B17 ;B16 = src1
MVKH .S2 0x40213333, B17 ;B16 = src1
MVKL .S2 0x33333333, B16 ;B18 = src2
MVKH .S2 0x33333333, B16 ;B18 = src2
;The address used is in internal memory
MVKL .S2 0x000E0000, B18 ;B18 = memory address
MVKH .S2 0x000E0000, B18 ;B18 = memory address
STNDW .D2 B17:B16,*B18++
;clear orignal value out of reg to show change
MVKL .S2 0xFFFFFFFF, B17 ;B16 = src1
MVKH .S2 0xFFFFFFFF, B17 ;B16 = src1
MVKL .S2 0xFFFFFFFF, B16 ;B18 = src2
MVKH .S2 0xFFFFFFFF, B16 ;B18 = src2
LDNDW .D2 *-B18[1],B17:B16
MVKL .S2 0x40213333, B24 ;B16 = src1
MVKH .S2 0x40213333, B24 ;B16 = src1
MVKL .S2 0x33333333, B25 ;B18 = src2
MVKH .S2 0x33333333, B25 ;B18 = src2
NOP 1 ;Delay Slot
CMPEQ .L2 B17, B24, B0 ;B0 = 1
[!B0] B .S1 ERRALU64 ;ERROR, if B0 !=0
NOP 5
CMPEQ .L2 B16, B25, B1
[!B1] B .S1 ERRALU65
NOP 5
;checking instruction STNW and LDNW
;Store and Load non-aligned word
MVKL .S2 0x00213333, B17 ;B16 = src1
MVKH .S2 0x00213333, B17 ;B16 = src1
;The address used is in internal memory
MVKL .S2 0x000E0000, B18 ;B18 = memory address
MVKH .S2 0x000E0000, B18 ;B18 = memory address
STNW .D2 B17,*B18++
MVKL .S2 0x000E0000, B18 ;B18 = memory address
MVKH .S2 0x000E0000, B18 ;B18 = memory address
;clear orignal value out of reg to show change
MVKL .S2 0x0FFFFFFF, B17 ;B16 = src1
MVKH .S2 0x0FFFFFFF, B17 ;B16 = src1
LDNW .D2 *B18[0],B17
MVKL .S2 0x00213333, B24 ;B16 = src1
MVKH .S2 0x00213333, B24 ;B16 = src1
NOP 2 ;Delay Slot
CMPEQ .L2 B17, B24, B0 ;B0 = 1
[!B0] B .S1 ERRALU66 ;ERROR, if B0 !=0
NOP 5
;checking for instruction CMPEQ2
;Compare if equal, packed 16-bit
MVKL .S2 0x11056E30, B16 ;B16 = src1
MVKH .S2 0x11056E30, B16 ;B16 = src1
MVKL .S2 0x11056E30, B18 ;B18 = src2
MVKH .S2 0x11056E30, B18 ;B18 = src2
MVKL .S2 0x00000003, B19 ;B19 = result
MVKH .S2 0x00000003, B19 ;B19 = result
CMPEQ2 .S2 B16, B18, B0
CMPEQ .L2 B19, B0, B0
[!B0] B .S1 ERRALU67 ;ERROR, if B0 !=0
NOP 5
;checking for instruction CMPEQ4
;Compare if equal, packed 8-bit
MVKL .S2 0x11056E30, B16 ;B16 = src1
MVKH .S2 0x11056E30, B16 ;B16 = src1
MVKL .S2 0x11166E40, B18 ;B18 = src2
MVKH .S2 0x11166E40, B18 ;B18 = src2
MVKL .S2 0x0000000A, B19 ;B19 = result
MVKH .S2 0x0000000A, B19 ;B19 = result
CMPEQ4 .S2 B16, B18, B0
CMPEQ .L2 B19, B0, B0
[!B0] B .S1 ERRALU67 ;ERROR, if B0 !=0
NOP 5
;checking for instruction CMPGT2
;Compare for grater than, packed 16-bit
MVKL .S2 0x11056E40, B16 ;B16 = src1
MVKH .S2 0x11056E40, B16 ;B16 = src1
MVKL .S2 0x11166E30, B18 ;B18 = src2
MVKH .S2 0x11166E30, B18 ;B18 = src2
MVKL .S2 0x00000001, B19 ;B19 = result
CMPGT2 .S2 B16, B18, B0
CMPEQ .L2 B19, B0, B0
[!B0] BNOP .S1 ERRALU68, 5 ;ERROR, if B0 !=0
;checking for instruction CMPGTU4
;Compare for grater than, unsigned packed 8-bit
;checking for instruction BNOP
;Branch using a displacement with NOP
MVKL .S2 0x11050340, B16 ;B16 = src1
MVKH .S2 0x11050340, B16 ;B16 = src1
MVKL .S2 0x09160730, B18 ;B18 = src2
MVKH .S2 0x09160730, B18 ;B18 = src2
MVKL .S2 0x00000009, B19 ;B19 = result
CMPGTU4 .S2 B16, B18, B0
CMPEQ .L2 B19, B0, B0
[!B0] BNOP .S1 ERRALU69, 5 ;ERROR, if B0 !=0
;checking for instruction ADDKPC 5-33
;add a signed 7-bit constant to program counter
MVKL .S2 0x0000000F, B19 ;B19 = result
B .S2 Test1
ADDKPC .S2 Test2 ,B17,4
Test2:
MVKL .S2 0x0000000F, B25 ;B16 = src1
CMPEQ .L2 B25, B19, B0
[!B0] BNOP .S1 ERRALU70, 5 ;ERROR, if B0 !=0
;checking for instruction BDEC
;Branch and Decrement
MVKL .S2 0x00000005, B17 ;B19 = result
BDEC .S2 Test3 ,B17
NOP 5
Test3:
MVKL .S2 0x00000004, B25 ;B16 = src1
CMPEQ .L2 B25, B17, B0
[!B0] BNOP .S1 ERRALU71, 5 ;ERROR, if B0 !=0
;checking for instruction BPOS
;Branch Positive
MVKL .S2 0x5, B17 ;B19 = result
MVKL .S2 0xFFFFFFF1, B18 ;B19 = result
BPOS .S2 Test4 ,B17
NOP 5
CMPEQ .L2 B18, B17, B0
[!B0] BNOP .S1 ERRALU73, 5 ;ERROR, if B0 !=0
NOP 5
Test4:
MVKL .S2 0x5, B25 ;B16 = src1
CMPEQ .L2 B25, B17, B0
[!B0] BNOP .S1 ERRALU72, 5 ;ERROR, if B0 !=0
;Since all my branches for errors are taken for [!B0] I need to
;set B0 equal to 0 so I dont get an overall error for Alu_6461
MVKL .S2 0x00000000, B0
;loading (or popping) appropriate registers from the stack
ENDALU:
LDW .D2 *++B15[1], A15 ;reverse order load
LDW .D2 *++B15[1], B13 ;from stack space
LDW .D2 *++B15[1], B12 ;this routine is
LDW .D2 *++B15[1], B11 ;responsible for
LDW .D2 *++B15[1], A11 ;loading app. values
LDW .D2 *++B15[1], B10 ;before returning to
LDW .D2 *++B15[1], A10 ;the calling routine
NOP 4
B .S2 B3 ;RETURN TO THE
NOP 5 ;MAIN CONTROL SHELL
;*
;*Error Handlers
;*
ERRALU1: MVKL .S2 21h, B0 ;SHIFT AND CMP
B .S2 ENDALU ;FAIL CODE
NOP 5
ERRALU2: MVKL .S2 22h, B0 ;LOGICAL INSTR.
B .S2 ENDALU ;FAIL CODE
NOP 5
ERRALU3: MVKL .S2 23h, B0 ;ADDITION INSTR.
B .S2 ENDALU ;FAIL CODE
NOP 5
ERRALU4: MVKL .S2 24h, B0 ;SUBTRACTION INSTR.
B .S2 ENDALU ;FAIL CODE
NOP 5
ERRALU5: MVKL .S2 25h, B0 ;SUBC FAIL CODE
B .S2 ENDALU
NOP 5
ERRALU6: MVKL .S2 26h, B0 ;SUB2 FAIL CODE
B .S2 ENDALU
NOP 5
;***************************************************************************
;Code for instruction-set extended for C64x support
;***************************************************************************
ERRALU7: MVKL .S2 0x9F001, B0 ;ABS2 FAIL CODE
MVKH .S2 0x9F001, B0
B .S2 ENDALU
NOP 5
ERRALU8: MVKL .S2 0x9F002, B0 ;ADD4 FAIL CODE
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