📄 alu_64x.asm
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[!B0] B .S1 ERRALU19 ;ERROR, if B0 !=0
NOP 5
;checking for instruction PACKHL2
;Pack 16 MSB, 16 LSB Into Packed 16-Bit
MVKL .S2 0x37894975, B19 ;B19 = result
MVKH .S2 0x37894975, B19 ;B19 = result
PACKHL2 .L2 B16, B18, B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU20 ;ERROR, if B0 !=0
NOP 5
;checking for instruction PACKHL2 using .S unit
PACKHL2 .S2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU37 ;ERROR, if B0 !=0
NOP 5
;checking for instruction PACKLH2
;Pack 16 MSB, 16 LSB Into Packed 16-Bit
MVKL .S2 0xF23A04B8, B19 ;B19 = result
MVKH .S2 0xF23A04B8, B19 ;B19 = result
PACKLH2 .L2 B16, B18, B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU21 ;ERROR, if B0 !=0
NOP 5
;checking for instruction PACKLH2 using .S2 unit
PACKLH2 .S2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU38 ;ERROR, if B0 !=0
NOP 5
;checking for instruction SHLMB
;Shift Left and Merge Byte
MVKL .S2 0xB8497537, B19 ;B19 = result
MVKH .S2 0xB8497537, B19 ;B19 = result
SHLMB .L2 B16, B18, B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU22 ;ERROR, if B0 !=0
NOP 5
;checking for instruction SHRMB
;Shift Right and Merge Byte
MVKL .S2 0x3A04B849, B19 ;B19 = result
MVKH .S2 0x3A04B849, B19 ;B19 = result
SHRMB .L2 B16, B18, B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU23 ;ERROR, if B0 !=0
NOP 5
;------>>checking for instruction SHRMB using .S unit
;Shift Right and Merge Byte
SHRMB .S2 B16, B18, B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU40 ;ERROR, if B0 !=0
NOP 5
;------>>checking for instruction SHLMB using .S unit
;Shift Right and Merge Byte
MVKL .S2 0xB8497537, B19 ;B19 = result
MVKH .S2 0xB8497537, B19 ;B19 = result
SHLMB .S2 B16, B18, B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU39 ;ERROR, if B0 !=0
NOP 5
;checking for instruction SUB4
;Subtract without saturation, signed packed 8-bit
MVKL .S2 0x33D1A9C5, B19 ;B19 = result
MVKH .S2 0x33D1A9C5, B19 ;B19 = result
SUB4 .L2 B16, B18, B20 ;Pack Low
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU25 ;ERROR, if B0 !=0
NOP 5
;checking for instruction SUBABS4
;subtract with ABS value, unsigned packed 8-bit
MVKL .S2 0x332FA93B, B19 ;B19 = result
MVKH .S2 0x332FA93B, B19 ;B19 = result
SUBABS4 .L2 B16, B18, B20 ;Pack Low
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU26 ;ERROR, if B0 !=0
NOP 5
;checking for instruction SUB2
;Two 16 Bit Interger Subtraction on Upper and Lower Register Halves
MVKL .S2 0xF23A6E30, B16 ;B16 src1
MVKH .S2 0xF23A6E30, B16 ;B16 src1
MVKL .S2 0x04B86980, B18 ;B18 src2
MVKH .S2 0x04B86980, B18 ;B18 src2
MVKL .S2 0xED8204b0, B19 ;B19 = result
MVKH .S2 0xED82B849, B19 ;B19 = result
SUB2 .L2 B16, B18, B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU24 ;ERROR, if B0 !=0
NOP 5
;checking for instruction SWAP2
;Swap bytes in each half-word (pseudo-operation)
MVKL .S2 0x3789F23A, B18 ;B18 src2
MVKH .S2 0x3789F23A, B18 ;B18 src2
MVKL .S2 0xF23A3789, B19 ;B19 = result
MVKH .S2 0xF23A3789, B19 ;B19 = result
SWAP2 .L2 B18,B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU27 ;ERROR, if B0 !=0
NOP 5
;checking for instruction SWAP2 using .S unit
;Swap bytes in each half-word (pseudo-operation)
SWAP2 .S2 B18,B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU43 ;ERROR, if B0 !=0
NOP 5
;checking for instruction SWAP4
;Swap bytes in each half-word (pseudo-operation)
MVKL .S2 0x9E526E30, B18 ;B18 src2
MVKH .S2 0x9E526E30, B18 ;B18 src2
MVKL .S2 0x529E306E, B19 ;B19 = result
MVKH .S2 0x529E306E, B19 ;B19 = result
SWAP4 .L2 B18,B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU28 ;ERROR, if B0 !=0
NOP 5
;checking for instruction UNPKHU4
;Unpack high unsigned packed 8-bit to unsigned packed 16-bit
MVKL .S2 0x9E526E30, B18 ;B18 src2
MVKH .S2 0x9E526E30, B18 ;B18 src2
MVKL .S2 0x009E0052, B19 ;B19 = result
MVKH .S2 0x009E0052, B19 ;B19 = result
UNPKHU4 .L2 B18,B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU29 ;ERROR, if B0 !=0
NOP 5
;checking for instruction UNPKHU4 using .S unit
;Unpack high unsigned packed 8-bit to unsigned packed 16-bit
UNPKHU4 .S2 B18,B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU44 ;ERROR, if B0 !=0
NOP 5
;checking for instruction UNPKLU4
;Unpack Low unsigned packed 8-bit to unsigned packed 16-bit
MVKL .S2 0x11056934, B18 ;B18 src2
MVKH .S2 0x11056934, B18 ;B18 src2
MVKL .S2 0x00690034, B19 ;B19 = result
MVKH .S2 0x00690034, B19 ;B19 = result
UNPKLU4 .L2 B18,B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU30 ;ERROR, if B0 !=0
NOP 5
;checking for instruction UNPKLU4 using .S unit
;Unpack Low unsigned packed 8-bit to unsigned packed 16-bit
UNPKLU4 .S2 B18,B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU44 ;ERROR, if B0 !=0
NOP 5
;checking for instruction MIN2
;Maximum, Signed Packed 16-bit
MVKL .S2 0x3789F23A, B16 ;B16 = src1 (ua_0, ua_1) Low
MVKH .S2 0x3789F23A, B16 ;B16 = src1 (ua_3, ua_2) High
MVKL .S2 0x04B84975, B18 ;B18 = src1 (ub_0, ub_1) Low
MVKH .S2 0x04B84975, B18 ;B18 = src1 (ub_3, ub_2) High
MVKL .S2 0x04B8F23A, B19 ;B19 = result
MVKH .S2 0x04B8F23A, B19 ;B19 = result
MIN2 .L2 B16, B18, B20 ;Maximum, Signed Packed 16-bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU12 ;ERROR, if B0 !=0
NOP 5
;checking for instruction ADD2 using .S unit
;Two 16-bit interger adds on upper and lower reg halves
MVKL .S2 0x002137E1, B16 ;B16 = src1
MVKH .S2 0x002137E1, B16 ;B16 = src1
MVKL .S2 0x039AE4B8, B18 ;B18 = src2
MVKH .S2 0x039AE4B8, B18 ;B18 = src2
MVKL .S2 0x03BB1C99, B19 ;B19 = result
MVKH .S2 0x03BB1C99, B19 ;B19 = result
ADD2 .S2 B16, B18, B20 ;
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU31 ;ERROR, if B0 !=0
NOP 5
;checking for instruction ADD2 using .D unit
;Two 16-bit interger adds on upper and lower reg halves
ADD2 .D2 B16, B18, B20 ;
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU32 ;ERROR, if B0 !=0
NOP 5
;checking for instruction SUB2 using .S unit
;Two 16-bit interger adds on upper and lower reg halves
MVKL .S2 0x11056E30, B16 ;B16 = src1
MVKH .S2 0x11056E30, B16 ;B16 = src1
MVKL .S2 0x11056980, B18 ;B18 = src2
MVKH .S2 0x11056980, B18 ;B18 = src2
MVKL .S2 0x000004B0, B19 ;B19 = result
MVKH .S2 0x000004B0, B19 ;B19 = result
SUB2 .S2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU33 ;ERROR, if B0 !=0
NOP 5
;checking for instruction SUB2 using .D unit
;Two 16-bit interger subtractions on upper and lower reg halves
SUB2 .S2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU34 ;ERROR, if B0 !=0
NOP 5
;--------->checking for instruction SHR2
;Shift right, signed packed 16-bit
MVKL .S2 0xA6E2C179, B16 ;B16 = src1
MVKH .S2 0xA6E2C179, B16 ;B16 = src1
MVKL .S2 0x14583B69, B18 ;B18 = src2
MVKH .S2 0x14583B69, B18 ;B18 = src2
MVKL .S2 0xFFD3FFE0, B19 ;B19 = result
MVKH .S2 0xFFD3FFE0, B19 ;B19 = result
SHR2 .S2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU41 ;ERROR, if B0 !=0
NOP 5
;checking for instruction SHRU2
;Shift right, unsigned packed 16-bit
MVKL .S2 0x00530060, B19 ;B19 = result
MVKH .S2 0x00530060, B19 ;B19 = result
SHRU2 .S2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU42 ;ERROR, if B0 !=0
NOP 5
;checking for instruction SPACK2
;Saturate and pack into signed packed 16 bit
MVKL .S2 0x3789F23A, B16 ;B16 = src1
MVKH .S2 0x3789F23A, B16 ;B16 = src1
MVKL .S2 0x04B84975, B18 ;B18 = src2
MVKH .S2 0x04B84975, B18 ;B18 = src2
MVKL .S2 0x7FFF7FFF, B19 ;B19 = result
MVKH .S2 0x7FFF7FFF, B19 ;B19 = result
SPACK2 .S2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU46 ;ERROR, if B0 !=0
NOP 5
;checking for instruction SPACKU4
;Saturate and pack into Unsigned packed 8-bit
MVKL .S2 0xFF00FFFF, B19 ;B19 = result
MVKH .S2 0xFF00FFFF, B19 ;B19 = result
SPACKU4 .S2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU47 ;ERROR, if B0 !=0
NOP 5
;checking for instruction OR using .L unit
;Saturate and pack into signed packed 16 bit
MVKL .S2 0x08A3A49F, B16 ;B16 = src1
MVKH .S2 0x08A3A49F, B16 ;B16 = src1
MVKL .S2 0x00FF375A, B18 ;B18 = src2
MVKH .S2 0x00FF375A, B18 ;B18 = src2
MVKL .S2 0x08FFB7DF, B19 ;B19 = result
MVKH .S2 0x08FFB7DF, B19 ;B19 = result
OR .L2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU48 ;ERROR, if B0 !=0
NOP 5
;checking for instruction OR using .S unit
OR .S2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU49 ;ERROR, if B0 !=0
NOP 5
;checking for instruction OR using .D unit
OR .D2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU50 ;ERROR, if B0 !=0
NOP 5
;checking for instruction XOR using .S unit
;Bitwise XOR
MVKL .S2 0x0721325A, B16 ;B16 = src1
MVKH .S2 0x0721325A, B16 ;B16 = src1
MVKL .S2 0x00190F12, B18 ;B18 = src2
MVKH .S2 0x00190F12, B18 ;B18 = src2
MVKL .S2 0x07383D48, B19 ;B19 = result
MVKH .S2 0x07383D48, B19 ;B19 = result
XOR .S2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU51 ;ERROR, if B0 !=0
NOP 5
;checking for instruction XOR using .D unit
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