📄 alu_64x.asm
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;/****************************************************************************\
; * Copyright (C) 2000 Texas Instruments Incorporated. *
; * All Rights Reserved *
; * *
; * GENERAL DISCLAIMER *
; * ------------------ *
; * All software and related documentation is provided "AS IS" and without *
; * warranty or support of any kind and Texas Instruments expressly disclaims*
; * all other warranties, express or implied, including, but not limited to, *
; * the implied warranties of merchantability and fitness for a particular *
; * purpose. Under no circumstances shall Texas Instruments be liable for *
; * any incidental, special or consequential damages that result from the *
; * use or inability to use the software or related documentation, even if *
; * Texas Instruments has been advised of the liability. *
;\****************************************************************************/
;This routine checks ALU operations
.ref _Inst_Test ;system initialization section
.ref main_shell ;the main control shell that calls
;all the subroutines
.def alu
.sect "aluchk"
;ARGUMENTS PASSED TO THIS ROUTINE
;A4 = 0FFFFh
;B4 = 5454h
;A6 = 5151h
;B6 = 3333h
;A8 = AAAAh
;B8 = 2222h
;A10 = FFFFFFFFh
;B10 = 00000003h
alu:
;saving (or pushing) appropriate registers onto the stack
STW .D2 A10, *B15--[1] ;decrementing SP
STW .D2 B10, *B15--[1] ;coping variables
STW .D2 A11, *B15--[1] ;onto the stack
STW .D2 B11, *B15--[1] ;A0-A9, B0-B9 are
STW .D2 B12, *B15--[1] ;saved by the
STW .D2 B13, *B15--[1] ;calling function
STW .D2 A15, *B15--[1]
;checking logic instructions
SHL .S2 A4, 4, B9 ;B9 = 000FFFF0h
SHL .S2 B9, 8, B9 ;B9 = 0FFFF000h
SHL .S2 B9, 4, B9 ;B9 = FFFF0000h
NOT .L2 B9, B11 ;B11 = 0000FFFFh
SUB .S2x B11, A4, B1 ;B1 = 00000000h
[B1] B .S2 ERRALU1
OR .L2x B9, A4, B0 ;B0 = FFFFFFFFh
NOT .L2 B0, B0 ;B0 = 00000000h
[B0] B .S2 ERRALU2 ;IF B0 != 0, THEN
NOP 5 ;ERROR OCCURS
OR .L2x B4, A6, B0 ;B0 = 5555h
XOR .S2 B0, B6, B0 ;B0 = 6666h
AND .L2x B0, A8, B0 ;B0 = 2222h
SUB .S2 B0, B8, B0 ;B0 = 0000h
[B0] B .S2 ERRALU2 ;IF B0 != 0, THEN
NOP 5 ;ERROR OCCURS
;B9 = FFFF0000h
SHR .S2 B9, 4, B12 ;B12 = FFFFF000h
SHR .S2 B12, 4, B12 ;B12 = FFFFFF00h
SHR .S2 B12, 4, B12 ;B12 = FFFFFFF0h
SHR .S2 B12, 4, B0 ;B0 = FFFFFFFFh
CMPEQ .L2x B0, A10, B0 ;B0 = 1h, if B0 = A10
CMPGT .L2 B10, B0, B1 ;B1 = 00000001h
CMPGT .L2 B0, B10, B1 ;B1 = 00000000h
[B1] B .S2 ERRALU1 ;IF B1 != 0, THEN
NOP 5 ;ERROR OCCURS
SHRU .S2 B9, 16, B9 ;B9 = 0000FFFFh
CMPEQ .L2x B9, A4, B1 ;B1 = 00000001h
SUB .L2 B1, 1, B1 ;B1 = 00000000h
[B1] B .S2 ERRALU1 ;ERROR, if B1 != 0
NOP 5
NOT .L2 B0, B0 ;B0 = FFFFFFFEh
NOT .L2 B10, B11 ;B11 = FFFFFFFch
CMPLT .L2 B11, B0, B1 ;B1 = 00000001h
CMPLT .L2 B0, B11, B1 ;B1 = 00000000h
[B1] B .S2 ERRALU1 ;IF B1 != 0, THEN
NOP 5 ;ERROR OCCURS
;*
;*Test Arithmetic Operations
;* B12 = FFFFFFF0h
MVKL .S1 0Fh, A9 ;A9 = 0000000Fh
OR .S2x A9, B12, B9 ;B9 = FFFFFFFFh
ADD .S2 B9, B9, B0 ;B0 = FFFFFFFEh
ADD .S2 B0, B9, B0 ;B0 = FFFFFFFDh
ABS .L1x B0, A7 ;B0 = 00000003h
ADD .L2x A7, B0, B0 ;B0 = 00000000h
[B0] B .S1 ERRALU3 ;IF B0 != 0, THEN
NOP 5 ;ERROR OCCURS
;checking for other instructions doing additions
MVKL .S2 002137E1h, B1 ;B1 = 000037E1h
MVKH .S2 002137E1h, B1 ;B1 = 002137E1h
MVKL .S2 039AE4B8h, B5
MVKH .S2 039AE4B8h, B5 ;B5 = 039AE4B8h
ADD2 .S2 B1, B5, B0 ;B0 = 03BB1C99h
ADD .L2 B1, B5, B2 ;B2 = 03BC1C99h
CMPGT .L2 B0, B2, B0 ;B0 = 00000000h
[B0] B .S1 ERRALU3 ;ERROR, if B0 != 0
NOP 5
MVKL .S2 15401, B9 ;B9 = 00003C29h
ADDK .S2 15401, B0 ;B0 = 00003c29h
SUB .L2 B0, B9, B0 ;B0 = 00000000h
[B0] B .S1 ERRALU3 ;IF B0 != 0, THEN
NOP 5 ;ERROR OCCURS
;checking for instructions performing substraction.
SUB .L1x B0, A10, A3 ;A3 = 00000001h
SUB .L1 A3, A10, A3 ;A3 = 00000002h
SUB .L1 A3, A10, A3 ;A3 = 00000003h
SUB .L2x A3, B10, B0 ;B0 = 00000000h
[B0] B .S2 ERRALU4
NOP 5
SUBAB .D1 A10, A8, A11 ;A11 = FFFF5555h
NEG .S2x A8, B7 ;B7 = FFFF5556h
ADD .S2x A10, B7, B13 ;B13 = FFFF5555h
CMPEQ .L2x A11, B13, B0 ;B0 = 1, if A11 = B13
SUB .L2 B0, 1, B0 ;B0 = 0
[B0] B .S2 ERRALU4 ;ERROR, if B0 != 0
NOP 5
SUBAH .D1 A10, A8, A11 ;A11 = FFFEAAABh
SHL .S2 B7, 1, B13 ;B13 = FFFEAAACh
ADD .S2x A10, B13, B13 ;B13 = FFFEAAABh
CMPEQ .L2x A11, B13, B0 ;B0 = 1, if A11 = B13
SUB .L2 B0, 1, B0 ;B0 = 0
[B0] B .S2 ERRALU4 ;ERROR, if B0 != 0
NOP 5
SUBAW .D1 A10, A8, A11 ;A11 = FFFD5557h
SHL .S2 B7, 2, B13 ;B13 = FFFD5558h
ADD .S2x A10, B13, B13 ;B13 = FFFD5557
CMPEQ .L2x A11, B13, B0 ;B0 = 1, if A11 = B13
SUB .L2 B0, 1, B0 ;B0 = 0
[B0] B .S2 ERRALU4 ;ERROR, if B0 != 0
NOP 5
;checking for conditional subtract and shift (Used for division)
MVKL .S1 01F63Fh, A3 ;A3 = 0000F63Fh
MVKH .S1 01F63Fh, A3 ;A3 = 0001F63Fh
MVKL .S2 021A31h, B2
MVKH .S2 021A31h, B2 ;B2 = 00021A31h
SUBC .L2x B2, A3, B13 ;B13 = 000047e5h
SUB .L1x B2, A3, A15 ;A15 = 000023F2h
CMPLT .L2x A15, 0h, B1 ;A15 is > 0 so B1 = 0
[!B1] SHL .S1 A15, 1, A15 ;A15 = 000047e4h
ADD .S1 A15, 01h, A15 ;A15 = 000047e5h
CMPEQ .L2x B13, A15, B0 ;B0 =1 , if A15 = B13
SUB .L2 B0, 01h, B0 ;B0 = 0
[B0] B .S1 ERRALU5 ;ERROR, if B0 != 0
NOP 5
;checking for instruction SUB2
SUB2 .S2x B6, A6, B9 ;B9 = 0000E1E2h
SUB .S2x B6, A6, B5 ;B5 = FFFFE1E2h
CMPLT .L2 B5, B9, B1 ;B1 = 1, if B5 < B9
SUB .S2 B1, 1h, B1 ;B1 = 0
[B1] B .S1 ERRALU6 ;ERROR, if B1 != 0
NOP 5
;*************************************************************************
;Code for instruction-set exteded for C64x support *
;checking for instruction ABS2 *
;*************************************************************************
MVKL .S2 0xFF684E3D, B16 ;B16 = 4E3Dh = -152 20029
MVKH .S2 0xFF684E3D, B16 ;B16 = FF68h
MVKL .S2 0x00984E3D, B18 ;B18 = 00984E3Dh
MVKH .S2 0x00984E3D, B18 ;B18 = 00984E3Dh
ABS2 .L2 B16, B17 ;B17 = 00984E3Dh = 152 20029
CMPEQ .L2 B17, B18, B0 ;B0 = 1
[!B0] B .S1 ERRALU7 ;ERROR, if B0 !=0
NOP 5
;Code for instruction-set exteded for C64x support
;checking for instruction ADD4
MVKL .S2 0xFF684E3D, B16 ;B16 = src1 (a_0, a_1) Low
MVKH .S2 0xFF684E3D, B16 ;B16 = src1 (a_3, a_2) High
MVKL .S2 0x3FF6F105, B18 ;B18 = src2 (b_0, b_1) Low
MVKH .S2 0x3FF6F105, B18 ;B18 = src2 (b_3, b_2) High
MVKL .S2 0x3E5E3F42, B19 ;B19 = (a_0 + b_0, a_1 + b_1) Low
MVKH .S2 0x3E5E3F42, B19 ;B19 = (a_3 + b_3, a_2 + b_2) High
ADD4 .L2 B16, B18, B20 ;Add 4 8-bit Pairs for Four 8-Bit Results
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU8 ;ERROR, if B0 !=0
NOP 5
;checking for instruction ANDN using .L unit
;Bit-Wise Logical AND Invert
MVKL .S2 0x195721AB, B16 ;B16 = src1 (a_0, a_1) Low
MVKH .S2 0x195721AB, B16 ;B16 = src1 (a_3, a_2) High
MVKL .S2 0x081C17E6, B18 ;B18 = src1 (a_0, a_1) Low
MVKH .S2 0x081C17E6, B18 ;B18 = src1 (a_3, a_2) High
MVKL .S2 0x11432009, B19 ;B19 = result
MVKH .S2 0x11432009, B19 ;B19 = result
ANDN .L2 B16, B18, B20 ;Bit-Wise Logical AND Invert
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU9 ;ERROR, if B0 !=0
NOP 5
;checking for instruction ANDN using .S unit
ANDN .S2 B16, B18, B20 ;Bit-Wise Logical AND Invert
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU59 ;ERROR, if B0 !=0
NOP 5
;checking for instruction ANDN using .D unit
ANDN .D2 B16, B18, B20 ;Bit-Wise Logical AND Invert
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU60 ;ERROR, if B0 !=0
NOP 5
;checking for instruction MAX2
;Maximum, Signed Packed 16-Bit
MVKL .S2 0x3789F23A, B16 ;B16 = src1 a_Low
MVKH .S2 0x3789F23A, B16 ;B16 = src1 a_High
MVKL .S2 0x04B84975, B18 ;B18 = src1 b_Low
MVKH .S2 0x04B84975, B18 ;B18 = src1 b_High
MVKL .S2 0x37894975, B19 ;B19 = result
MVKH .S2 0x37894975, B19 ;B19 = result
MAX2 .L2 B16, B18, B20 ;Maximum, Signed Packed 16-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU10 ;ERROR, if B0 !=0
NOP 5
;checking for instruction MAXU4
;Maximum, UnSigned Packed 8-Bit
MVKL .S2 0x3789F23A, B16 ;B16 = src1 (ua_0, ua_1) Low
MVKH .S2 0x3789F23A, B16 ;B16 = src1 (ua_3, ua_2) High
MVKL .S2 0x04B84975, B18 ;B18 = src1 (ub_0, ub_1) Low
MVKH .S2 0x04B84975, B18 ;B18 = src1 (ub_3, ub_2) High
MVKL .S2 0x37B8F275, B19 ;B19 = result
MVKH .S2 0x37B8F275, B19 ;B19 = result
MAXU4 .L2 B16, B18, B20 ;Maximum, UnSigned Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU11 ;ERROR, if B0 !=0
NOP 5
;checking for instruction MINU4
;Maximum, Signed Packed 16-bit
MVKL .S2 0x0489493A, B19 ;B19 = result
MVKH .S2 0x0489493A, B19 ;B19 = result
MINU4 .L2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU13 ;ERROR, if B0 !=0
NOP 5
;checking for instruction PACKH4
;Pack High Bytes of Four Half-Words Into Packed 8-Bit
MVKL .S2 0x37F20449, B19 ;B19 = result
MVKH .S2 0x37F20449, B19 ;B19 = result
PACKH4 .L2 B16, B18, B20 ;Pack High Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU14 ;ERROR, if B0 !=0
NOP 5
;checking for instruction PACKL4
;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
MVKL .S2 0x893AB875, B19 ;B19 = result
MVKH .S2 0x893AB875, B19 ;B19 = result
PACKL4 .L2 B16, B18, B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU15 ;ERROR, if B0 !=0
NOP 5
;checking for instruction PACKHL2
;Pack 16 MSB, 16LSB into PACKED 16-Bit
MVKL .S2 0x37894975, B19 ;B19 = result
MVKH .S2 0x37894975, B19 ;B19 = result
PACKHL2 .L2 B16, B18, B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU16 ;ERROR, if B0 !=0
NOP 5
;checking for instruction PACKH2
;Pack 16 MSB, 16 MSB into Packed 16-Bit
MVKL .S2 0x378904B8, B19 ;B19 = result
MVKH .S2 0x378904B8, B19 ;B19 = result
PACKH2 .L2 B16, B18, B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU17 ;ERROR, if B0 !=0
NOP 5
;checking for instruction PACKH2 using .S unit
PACKH2 .S2 B16, B18, B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU36 ;ERROR, if B0 !=0
NOP 5
;checking for instruction PACK2
;Pack 16 MSB, 16 MSB into Packed 16-Bit
MVKL .S2 0xF23A4975, B19 ;B19 = result
MVKH .S2 0xF23A4975, B19 ;B19 = result
PACK2 .L2 B16, B18, B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU18 ;ERROR, if B0 !=0
NOP 5
;checking for instruction PACK2 using .S unit
;Pack 16 MSB, 16 MSB into Packed 16-Bit
PACK2 .S2 B16, B18, B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRALU35 ;ERROR, if B0 !=0
NOP 5
;checking for instruction PACKL2
;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
MVKL .S2 0xF23A4975, B19 ;B19 = result
MVKH .S2 0xF23A4975, B19 ;B19 = result
PACK2 .L2 B16, B18, B20 ;Pack Low Bytes of Four Half-Words Into Packed 8-Bit
CMPEQ .L2 B19, B20, B0 ;B0 = 1
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