bit.asm

DSP芯片自检测程序

;/****************************************************************************\
; *           Copyright (C) 2000 Texas Instruments Incorporated.             *
; *                           All Rights Reserved                            *
; *                                                                          *
; * GENERAL DISCLAIMER                                                       *
; * ------------------                                                       *
; * All software and related documentation is provided "AS IS" and without   *
; * warranty or support of any kind and Texas Instruments expressly disclaims*
; * all other warranties, express or implied, including, but not limited to, *
; * the implied warranties of merchantability and fitness for a particular   *
; * purpose.  Under no circumstances shall Texas Instruments be liable for   *
; * any incidental, special or consequential damages that result from the    *
; * use or inability to use the software or related documentation, even if   *
; * Texas Instruments has been advised of the liability.                     *
;\****************************************************************************/

;This routine checks BIT operations.

		.ref _Inst_Test     ;system initialization section
		.ref main_shell ;the main control shell that calls 
				;all the subroutines
		.def bitmgmt



		.sect   "bitchk"

;ARGUMENTS PASSED TO THIS ROUTINE
;A4 = 0FFFFh
;B4 = 5454h 
;A6 = 5151h
;B6 = 3333h
;A8 = AAAAh
;B8 = 2222h
;A10 = FFFFFFFFh
;B10 = 00000003h 
		
bitmgmt:

;saving (or pushing) appropriate registers onto the stack

		STW     .D2     A10, *B15--[1]  ;decrementing SP
		STW     .D2     B10, *B15--[1]  ;coping variables
		STW     .D2     A11, *B15--[1]  ;onto the stack
		STW     .D2     B11, *B15--[1]  ;A0-A9, B0-B9 are 
		STW     .D2     B12, *B15--[1]  ;saved by the
		STW     .D2     A14, *B15--[1]  ;calling function

;***********************************************************
;* checking CLR instruction to clear each bit (one by one) *
;* in a register from A side (A10).                        *
;***********************************************************
		MVKL     .S2     0h, B5          ;csta/cstb specified
		MVKL     .S2     21h, B9         ;incr. bit to be cleared
		MVKL     .S2     32, B2          ;counter for thru 32 bits
		MVKL    .S1     1h, A7

;**************************************************************
;* Each bit in the register is cleared using CLR instruction. *
;* Another way of doing it is to X0R between A7 (1h) and A10  *
;* which contains all F's. Each time thru the loop, a higher  *
;* bit is cleared (0 first time then 1st bit the second time) *
;* while A7 is also shifted left and XORed every time with    *
;* A10. Essentially they both have same result and thus each  *
;* time they are subtracted from one another and if B1 = 0    *
;* then no ERROR occurs.                                      *
;**************************************************************

CLRLOOP1:       
		CLR     .S2     A10, B5, B7     ;clear bit in A10 -> B7
		XOR     .S1     A7, A10, A9     ;XOR gives same result                  
		SUB     .L2     A9, B7, B1      ;A9 and B7 should be EQ
	[B1]    B       .S2     ERRBIT1         ;If not, then ERROR
		SHL     .S1     A7, 1, A7       ;A7 changes at each iter.
		ADD     .L2     B5, B9, B5      ;B5 changes every time
		SUB     .L2     B2, 1, B2       ;counter is decremented
		NOP     2                       ;3/5 delay slots are 
						;filled by useful instr.
	[B2]    B       .S2     CLRLOOP1        ;stay in loop till B2=0
		NOP     5                       ;delay slots - not opt.

;***********************************************************
;* Functionality test for a different register             *
;* checking CLR instruction to clear each bit (one by one) *
;* in a register from B side (B12).                        *
;***********************************************************
		MVKL    .S2     0h, B5          ;csta/cstb
		MVKL    .S2     21h, B9
		MVKL    .S2     32, B2          ;counter
		MVKL    .S1     1h, A7
		MV      .L2x    A10, B12

CLRLOOP2:
		CLR     .S2     B12, B5, B7     
		XOR     .S1x    A7, B12, A9                     
		SUB     .L2x    A9, B7, B1
	[B1]    B       .S2     ERRBIT1
		SHL     .S1     A7, 1, A7
		ADD     .L2     B5, B9, B5
		SUB     .L2     B2, 1, B2
		NOP     2       
	[B2]    B       .S2     CLRLOOP2
		NOP     5

;**************************************************
;* The following segment test the CLR instruction *
;* using constants instead of registers.          *
;**************************************************
		MVKL     .S2     0FFF0000Fh, B11         ;prelim. setup
		MVKH    .S2     0FFF0000Fh, B11         ;known result
		CLR     .S1     A10,4,19, A11           ;clr bits 4-19
		CMPEQ   .L2x    B11, A11, B1            ;if eq, B1 =1
		SUB     .S2     B1, 1, B1               ;B1 - 1 -> B1
	[B1]    B       .S2     ERRBIT1                 ;if B1 !=0 then
		NOP     5                               ;ERROR 

;*************************************************************
;* Checking for EXT for each bit of a register. It extracts  *
;* a bit field specified either by constants or 10 LSBs of   *
;* another register. EXT or EXTU .unit src2, csta, cstb, dst *
;*************************************************************
		MVKL    .S2     0FFFh, B5       ;increment value
		MVKL    .S2     0FFFh, B9       ;csta/cstb in reg
		MVKL    .S2     32, B2          ;counter=#ofbits in reg
		MVKL    .S1     1h, A9          ;initial value

;***************************************************************
;* EXTU instruction doesn't sign extend. Each bit is extracted *
;* and put into another register. This can also be achieved by *
;* left shifting A9 by 1 each time thru the loop. EXTU can     *
;* be used to extract a bit field. In that case, you can copy  *
;* a known results into a register and compare it against the  *
;* result generated by the EXTU/EXT instruction.               *
;***************************************************************

EXTLOOP:
		EXTU    .S2     B12, B9, B7     ;gets the lsb
		SUB     .L2x    A9, B7, B1      ;A9 = 1h, B1 =0
	[B1]    B       .S2     ERRBIT2         ;ERROR if B1 != 0
		ADD     .L2     B9, B5, B9      ;incr. the bit to EXT
		SUB     .L2     B2, 1, B2       ;decr. the counter
		SHL     .S1     A9, 1, A9       ;shifting A9 by 1
		NOP     2                       ;3/5 slots filled with
						;useful instructions
	[B2]    B       .S2     EXTLOOP         ;Loop till B2 = 0
		NOP     5

;**************************************************************
;* checking for EXTU/EXT with constants. EXT will sign extend *
;* the result while EXTU will not.                            *
;* B6 = 00003333h                                             *
;* 7 -> 13 bits are to be extracted = 110 0110b               *
;* EXT sign extends = FFFFFFE6h, EXTU doesn sign extend = 66h *
;**************************************************************
		MVKL    .S2     66h, B1         ;known result EXTU
		MVKL    .S2     0FFFFFFE6h, B5  ;known result EXT

		EXTU    .S2     B6, 18, 25, B11 ;B11 = 00000066h
		EXT     .S2     B6, 18, 25, B12 ;B12 = FFFFFFE6h
		CMPEQ   .L2     B11, B1, B1     ;B1 = 1, if eq
		SUB     .S2     B1, 1, B1       ;B1 = 0
	[B1]    B       .S2     ERRBIT2         ;ERROR if B1 != 0
		CMPEQ   .L2     B12, B5, B2     ;B2 = 1, if eq
		SUB     .L2     B2, 1, B2       ;B2 = 0
		NOP     3                       ;3/5 delay slots
	[B2]    B       .S2     ERRBIT2         ;ERROR if B2 != 0
		NOP     5                       ;normal 5 delay slots

;*****************************************************************
;* LMBD checks for the left most bit detection. You can specify  *
;* whether to look for 1 or 0 by using a register. The number of *
;* bits to the left of the first 1 or 0 when searching for a 1   *
;* or 0, respectively, is placed in a destination register.      *
;*                                                               *
;* This part of the routine uses two registers to store          *
;* pre-determined known results. Then LMBD instruction results   *
;* and those KNOWN results are compared.                         *
;*****************************************************************
;preliminary setup
		MVKL    .S1     0FFFFFFEEh, A5  ;test subject
		MVKH    .S1     0FFFFFFEEh, A5  
		MV      .S2     A6, B7          ;B7 = 05151h

;putting KNOWN results into registers 
		MVKL    .S2     1Bh, B1         ;B1 = 1Bh = 27bits 
		MVKL    .S2     11h, B2         ;B2 = 11h = 17bits

;**********************************
;* LMBD (.unit) src1, src2, dst   *
;* LSB of src1 determines whether *
;* to search for 1 or 0           *
;**********************************
;* A5 = FFFFFFEEh
;* B4 = 05454h
;* B7 = 05151h

		LMBD    .L1     A5, A5, A7      ;A7 = 1Bh = 27bits
		LMBD    .L2     B7, B4, B9      ;B9 = 11h = 17bits
		CMPEQ   .L2x    B1, A7, B1      ;B1 = 1, if A7 = B1
		SUB     .S2     B1, 1, B1       ;B1 = 0
	[B1]    B       .S1     ERRBIT3         ;ERROR, IF B1 != 0
		CMPEQ   .L2     B2, B9, B2      ;B2 = 1, if B9 = B2
		SUB     .S2     B2, 1, B2       ;B2 = 0
		NOP     3                       ;2/5 delay slots are
						;used by useful instr.
	[B2]    B       .S1     ERRBIT3         ;ERROR, IF B2 != 0
		NOP     5       

;********************************************************
;* testing the NORM instruction for some of the         *
;* passed arguments (even registers A4-A10 and B4-B10)  *         
;********************************************************
;A4 = 0FFFFh            = redundant sign bits = 15      *
;B4 = 5454h             = 16                            *
;B6 = 3333h             = 17                            *
;A10 = FFFFFFFFh        = 31                            *
;B10 = 00000003h        = 29                            *
;preliminary setup before the test - EXPECTED results   *
;to compare with the ouput of the NORM instruction on   *
;a particular register.                                 *
;********************************************************
		MVKL    .S1     0Fh, A2         ;A2 = 15 bits
		MVKL    .S1     10h, A7         ;A7 = 16  "
		MVKL    .S1     11h, A9         ;A9 = 17  "
		MVKL    .S2     1Fh, B9         ;B9 = 31  "
		MVKL    .S1     1Dh, A14        ;A14 = 29 "

;*******************************************************
;* actual test segment                                 *
;* 1 Branch delay slot is filled by useful instruction *
;* in each case.                                       *
;*******************************************************
		NORM    .L1     A4, A5          ;A5 = 0Fh
		CMPEQ   .L1     A5, A2, A2      ;A2 = 1, if A2 = A5
		SUB     .S1     A2, 1, A2       ;A2 = 0
	[A2]    B       .S1     ERRBIT4         ;ERROR, if A2 != 0
		NORM    .L2     B4, B5          ;B5 = 10h
		NOP     4                       
		CMPEQ   .L1x    A7, B5, A2      ;A2 = 1, if B5 = A7
		SUB     .S1     A2, 1, A2       ;A2 = 0
	[A2]    B       .S1     ERRBIT4         ;ERROR, if A2 != 0
		NORM    .L2     B6, B7          ;B7 = 11h
		NOP     4
		CMPEQ   .L1x    A9, B7, A2      ;A2 = 1, if B7 = A9
		SUB     .S1     A2, 1, A2       ;A2 = 0
	[A2]    B       .S1     ERRBIT4         ;ERROR, if A2 != 0
		NORM    .L1     A10, A11        ;A11 = 1Fh
		NOP     4
		CMPEQ   .L1x    A11, B9, A2     ;A2 = 1, if A11 = B9
		SUB     .S1     A2, 1, A2       ;A2 = 0
	[A2]    B       .S2     ERRBIT4         ;ERROR, if A2 != 0
		NORM    .L2     B10, B11        ;B11 = 1Dh
		NOP     4
		CMPEQ   .L1x    B11, A14, A2    ;A2 = 1, B11 = A14
		SUB     .S1     A2, 1, A2       ;A2 = 0
	[A2]    B       .S2     ERRBIT4         ;ERROR, if A2 != 0
		NOP     5                       ;in this case, there
						;no useful instr. to
						;to fill delay slots

;**********************************************************
;* Testing the SET instruction                            *
;* It sets a bit or a bit field to 1 specified either by  *
;* constants or a register. In this case, it starts out   *
;* with a zeroED register and set each bit one by one     *
;* resulting in FFFFFFFFh which is written to B7. cstb    *
;* increments while csta remains set to zero.             *
;**********************************************************

		MVKL    .S2     0h, B5          ;initial csta/cstb
		MVKL    .S2     01h, B9         ;increment cstb 
		MVKL    .S2     32, B2          ;loop counter
		MVKL    .S1     0h, A7
SETLOOP:
		SET     .S2     A7, B5, B7      ;B7 = FFFFFFFFh at end
		ADD     .L2     B5, B9, B5      ;incrementing cstb
		SUB     .L2     B2, 1, B2       ;decrementing counter
	[B2]    B       .S2     SETLOOP         ;loop till B2 = 0
		NOP     3                       ;2/5 slots useful instr.
		CMPEQ   .L2x    B7, A10, B1     ;B1 = 1, if B7 = A10
		SUB     .L2     B1, 1, B1       ;B1 = 0
	[B1]    B       .S2     ERRBIT5         ;ERROR, if B1 != 0
		NOP     5

;*****************************************
;checking SET instruction with constants *
;A7 = 00000000h A5 = 0000FFFFh           *
;*****************************************
		SET     .S1     A7, 0, 15, A5   ;A5 = 0FFFFh
		CMPEQ   .L1     A5, A4, A2      ;A2 = 1, if A5 = A4
		SUB     .L1     A2, 1, A2       ;A2 = 0
	[A2]    B       .S1     ERRBIT5         ;ERROR, if A2 != 0
		NOP     5

;loading (or popping) appropriate registers from the stack
ENDBIT:
		LDW     .D2     *++B15[1], A14  ;reverse order load
		LDW     .D2     *++B15[1], B12  ;this routine is 
		LDW     .D2     *++B15[1], B11  ;responsible for 
		LDW     .D2     *++B15[1], A11  ;loading app. values
		LDW     .D2     *++B15[1], B10  ;before returning to
		LDW     .D2     *++B15[1], A10  ;the calling routine
		NOP     4

		B       .S2     B3              ;RETURN TO THE
		NOP     5                       ;MAIN CONTROL SHELL

;*
;* Error Handler for BIT Routine
;*

ERRBIT1:        MVKL    .S2     41h, B0         ;CLR Error
		B       .S2     ENDBIT
		NOP     5

ERRBIT2:       MVKL    .S2     42h, B0          ;EXTU Error
		B       .S2     ENDBIT
		NOP     5

ERRBIT3:       MVKL    .S2     43h, B0          ;LMBD Error
		B       .S2     ENDBIT
		NOP     5

ERRBIT4:       MVKL    .S2     44h, B0          ;NORM Error
		B       .S2     ENDBIT
		NOP     5

ERRBIT5:       MVKL    .S2     45h, B0          ;SET ERROR
		B       .S2     ENDBIT
		NOP     5