📄 mult_64x.asm
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CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT18 ;ERROR, if B0 !=0
NOP 5
;checking instruction DOTPU4
;Dot Product, Unsigned Packed 8-bit
MVKL .S2 0x0000C54A, B19 ;B19 = result
MVKH .S2 0x0000C54A, B19 ;B19 = result
DOTPU4 .M2 B16, B18, B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT19 ;ERROR, if B0 !=0
NOP 5
;checking instruction GMPY4 (Polynomial =0x11d)
;Galois Field Multiply, Packed 8-bit
MVKL .S2 0x45230001, B16 ;B16 = src1
MVKH .S2 0x45230001, B16 ;B16 = src1
MVKL .S2 0x57340001, B18 ;B18 = src2
MVKH .S2 0x57340001, B18 ;B18 = src2
MVKL .S2 0x72920001, B19 ;B19 = result
MVKH .S2 0x72920001, B19 ;B19 = result
GMPY4 .M2 B16, B18, B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT20 ;ERROR, if B0 !=0
NOP 5
;checking instruction GMPY4 (field size is 256)
;Galois Field Multiply
MVKL .S2 0xFFFE021F, B16 ;B16 = src1
MVKH .S2 0xFFFE021F, B16 ;B16 = src1
MVKL .S2 0xFFFE0201, B18 ;B18 = src2
MVKH .S2 0xFFFE0201, B18 ;B18 = src2
MVKL .S2 0xE2E3041F, B19 ;B19 = result
MVKH .S2 0xE2E3041F, B19 ;B19 = result
GMPY4 .M2 B16, B18, B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT21 ;ERROR, if B0 !=0
NOP 5
;checking instruction MPY2
;Multiply Signed by Signed, Packed 16-bit
MVKL .S2 0x6A321193, B16 ;B16 = src1
MVKH .S2 0x6A321193, B16 ;B16 = src1
MVKL .S2 0xB1746CA4, B18 ;B18 = src2
MVKH .S2 0xB1746CA4, B18 ;B18 = src2
MVKL .S2 0xDF6AB0A8, B19 ;B19 = result_1
MVKH .S2 0xDF6AB0A8, B19 ;B19 = result_1
MVKL .S2 0x0775462C, B22 ;B19 = result_2
MVKH .S2 0x0775462C, B22 ;B19 = result_2
MPY2 .M2 B16, B18, B21:B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B21, B0 ;B0 = 1
[!B0] B .S1 ERRMULT22 ;ERROR, if B0 !=0
NOP 5
CMPEQ .L2 B22, B20, B1
[!B1] B .S1 ERRMULT23
NOP 5
;checking instruction MPYHI
;Multiply 16 MSB * 32-bit into 64-bit result
MVKL .S2 0xFFFFDF6A, B19 ;B19 = result_1
MVKH .S2 0xFFFFDF6A, B19 ;B19 = result_1
MVKL .S2 0xDDB92008, B22 ;B19 = result_2
MVKH .S2 0xDDB92008, B22 ;B19 = result_2
MPYHI .M2 B16, B18, B21:B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B21, B0 ;B0 = 1
[!B0] B .S1 ERRMULT24 ;ERROR, if B0 !=0
NOP 5
CMPEQ .L2 B22, B20, B1
[!B1] B .S1 ERRMULT25
NOP 5
;checking instruction MPYIH
;Multiply 32 * High 16-bit into 64-bit result (pseudo-operation)
MVKL .S2 0xFFFFDF6A, B19 ;B19 = result_1
MVKH .S2 0xFFFFDF6A, B19 ;B19 = result_1
MVKL .S2 0xAB43999C, B22 ;B19 = result_2
MVKH .S2 0xAB43999C, B22 ;B19 = result_2
MPYIH .M2 B16, B18, B21:B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B21, B0 ;B0 = 1
[!B0] B .S1 ERRMULT26 ;ERROR, if B0 !=0
NOP 5
CMPEQ .L2 B22, B20, B1
[!B1] B .S1 ERRMULT27
NOP 5
;checking instruction MPYHIR
;Multiply 16 MSB * 32-bit, shifted by 15 to produce a rounded 32-bit result
MVKL .S2 0x12343497, B16 ;B16 = src1
MVKH .S2 0x12343497, B16 ;B16 = src1
MVKL .S2 0x21FF50A7, B18 ;B18 = src2
MVKH .S2 0x21FF50A7, B18 ;B18 = src2
MVKL .S2 0x04D5B710, B19 ;B19 = result_1
MVKH .S2 0x04D5B710, B19 ;B19 = result_1
MPYHIR .M2 B16, B18, B21
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B21, B0 ;B0 = 1
[!B0] B .S1 ERRMULT28 ;ERROR, if B0 !=0
NOP 5
;checking instruction MPYIHR
;Multiply 32-bit * high 16-bit, shifted by 15 to produce a rounded 32-bit result
;(Pseudo-Operation)
MVKL .S2 0x04D5B990, B19 ;B19 = result_1
MVKH .S2 0x04D5B990, B19 ;B19 = result_1
MPYIHR .M2 B16, B18, B21
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B21, B0 ;B0 = 1
[!B0] B .S1 ERRMULT29 ;ERROR, if B0 !=0
NOP 5
;checking instruction MPYLI
;Multiply 16 LSB * 32-bit into 64-bit result
MVKL .S2 0x000006FB, B19 ;B19 = result_1
MVKH .S2 0x000006FB, B19 ;B19 = result_1
MVKL .S2 0xE9FA7E81, B22 ;B19 = result_2
MVKH .S2 0xE9FA7E81, B22 ;B19 = result_2
MPYLI .M2 B16, B18, B21:B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B21, B0 ;B0 = 1
[!B0] B .S1 ERRMULT30 ;ERROR, if B0 !=0
NOP 5
CMPEQ .L2 B22, B20, B1
[!B1] B .S1 ERRMULT31
NOP 5
;checking instruction MPYIL
;Multiply 32 * Low 16-bit into 64-bit result (pseudo-operation)
MVKL .S2 0x000006FB, B19 ;B19 = result_1
MVKH .S2 0x000006FB, B19 ;B19 = result_1
MVKL .S2 0xE9FA7E81, B22 ;B19 = result_2
MVKH .S2 0xE9FA7E81, B22 ;B19 = result_2
MPYLI .M2 B16, B18, B21:B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B21, B0 ;B0 = 1
[!B0] B .S1 ERRMULT32 ;ERROR, if B0 !=0
NOP 5
CMPEQ .L2 B22, B20, B1
[!B1] B .S1 ERRMULT33
NOP 5
;checking instruction MPYLIR
;Multiply 16 LSB * 32-bit, shifited by 15 to produce a rounded 32-bit result
MVKL .S2 0x0DF7D3F5, B19 ;B19 = result_1
MVKH .S2 0x0DF7D3F5, B19 ;B19 = result_1
MPYLIR .M2 B16, B18, B21
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B21, B0 ;B0 = 1
[!B0] B .S1 ERRMULT34 ;ERROR, if B0 !=0
NOP 5
;checking instruction MPYILR
;Multiply 32-bit * Low 16, shifited by 15 to produce a rounded 32-bit result
;(Pseudo-Operation)
MVKL .S2 0x0B7860FB, B19 ;B19 = result_1
MVKH .S2 0x0B7860FB, B19 ;B19 = result_1
MPYILR .M2 B16, B18, B21
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B21, B0 ;B0 = 1
[!B0] B .S1 ERRMULT35 ;ERROR, if B0 !=0
NOP 5
;checking instruction MPYSU4
;Multiply Signed by Unsigned packed, 8-bit
MVKL .S2 0x6A321193, B16 ;B16 = src1
MVKH .S2 0x6A321193, B16 ;B16 = src1
MVKL .S2 0xB1746CA4, B18 ;B18 = src2
MVKH .S2 0xB1746CA4, B18 ;B18 = src2
MVKL .S2 0x494A16A8, B19 ;B19 = result_1
MVKH .S2 0x494A16A8, B19 ;B19 = result_1
MVKL .S2 0x072CBA2C, B22 ;B22 = result_2
MVKH .S2 0x072CBA2C, B22 ;B22 = result_2
MPYSU4 .M2 B16, B18, B21:B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B21, B0 ;B0 = 1
[!B0] B .S1 ERRMULT36 ;ERROR, if B0 !=0
NOP 5
CMPEQ .L2 B22, B20, B1
[!B1] B .S1 ERRMULT37
NOP 5
;checking instruction MPYUS4
;Multiply Signed by Unsigned packed, 8-bit
;(Pseudo-Operation)
MVKL .S2 0xDF4A16A8, B19 ;B19 = result_1
MVKH .S2 0xDF4A16A8, B19 ;B19 = result_1
MVKL .S2 0x072CCB2C, B22 ;B19 = result_2
MVKH .S2 0x072CCB2C, B22 ;B19 = result_2
MPYUS4 .M2 B16, B18, B21:B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B21, B0 ;B0 = 1
[!B0] B .S1 ERRMULT38 ;ERROR, if B0 !=0
NOP 5
CMPEQ .L2 B22, B20, B1
[!B1] B .S1 ERRMULT39
NOP 5
;checking instruction MPYU4
;Multiply Signed by Unsigned packed, 8-bit
MVKL .S2 0x6832C193, B16 ;B16 = src1
MVKH .S2 0x6832C193, B16 ;B16 = src1
MVKL .S2 0xB1742CAB, B18 ;B18 = src2
MVKH .S2 0xB1742CAB, B18 ;B18 = src2
MVKL .S2 0x47E816A8, B19 ;B19 = result_1
MVKH .S2 0x47E816A8, B19 ;B19 = result_1
MVKL .S2 0x212C6231, B22 ;B22 = result_2
MVKH .S2 0x212C6231, B22 ;B22 = result_2
MPYU4 .M2 B16, B18, B21:B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B21, B0 ;B0 = 1
[!B0] B .S1 ERRMULT40 ;ERROR, if B0 !=0
NOP 5
CMPEQ .L2 B22, B20, B1
[!B1] B .S1 ERRMULT41
NOP 5
;checking instruction MVD
;Move from register to register, delayed
MVKL .S1 0x6832C193, A20 ;A20 = src1
MVKH .S1 0x6832C193, A20 ;A20 = src1
MVKL .S2 0x6832C193, B18 ;B18 = result
MVKH .S2 0x6832C193, B18 ;B18 = result
MVD .M2X A20, B21
NOP 4 ;Delay Slot
CMPEQ .L2 B18, B21, B0 ;B0 = 1
[!B0] B .S1 ERRMULT42 ;ERROR, if B0 !=0
NOP 5
;checking instruction ROTL
;Multiply Signed by Unsigned packed, 8-bit
MVKL .S2 0xA6E2C179, B16 ;B16 = src1
MVKH .S2 0xA6E2C179, B16 ;B16 = src1
MVKL .S2 0x14583B69, B18 ;B18 = src2
MVKH .S2 0x14583B69, B18 ;B18 = src2
MVKL .S2 0xC582F34D, B19 ;B19 = result_1
MVKH .S2 0xC582F34D, B19 ;B19 = result_1
ROTL .M2 B16, B18, B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT43 ;ERROR, if B0 !=0
NOP 5
;checking instruction SHFL
;Shuffle
MVKL .S2 0xB1746CA4, B20 ;A20 = src1
MVKH .S2 0xB1746CA4, B20 ;A20 = src1
MVKL .S2 0x9E526E30, B18 ;B18 = result
MVKH .S2 0x9E526E30, B18 ;B18 = result
SHFL .M2 B20, B21
NOP 4 ;Delay Slot
CMPEQ .L2 B18, B21, B0 ;B0 = 1
[!B0] B .S1 ERRMULT44 ;ERROR, if B0 !=0
NOP 5
;checking instruction SMPY2
;Multiply Signed by Signed, with left shift and saturate, packed 16-bit
MVKL .S2 0x6A321193, B16 ;B16 = src1
MVKH .S2 0x6A321193, B16 ;B16 = src1
MVKL .S2 0xB1746CA4, B18 ;B18 = src2
MVKH .S2 0xB1746CA4, B18 ;B18 = src2
MVKL .S2 0xBED56150, B19 ;B19 = result_1
MVKH .S2 0xBED56150, B19 ;B19 = result_1
MVKL .S2 0x0EEA8C58, B22 ;B22 = result_2
MVKH .S2 0x0EEA8c58, B22 ;B22 = result_2
SMPY2 .M2 B16, B18, B21:B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B21, B0 ;B0 = 1
[!B0] B .S1 ERRMULT45 ;ERROR, if B0 !=0
NOP 5
CMPEQ .L2 B22, B20, B1
[!B1] B .S1 ERRMULT46
NOP 5
;checking instruction SSHVL
;Variable shift left, signed
MVKL .S2 0xFFFFF000, B16 ;B16 = src1
MVKH .S2 0xFFFFF000, B16 ;B16 = src1
MVKL .S2 0xFFFFFFE1, B18 ;B18 = src2
MVKH .S2 0xFFFFFFE1, B18 ;B18 = src2
MVKL .S2 0xFFFFFFFF, B19 ;B19 = result_1
MVKH .S2 0xFFFFFFFF, B19 ;B19 = result_1
SSHVL .M2 B16, B18, B20
NOP 4 ;Delay Slot
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