📄 mult_64x.asm
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;/****************************************************************************\
; * Copyright (C) 2000 Texas Instruments Incorporated. *
; * All Rights Reserved *
; * *
; * GENERAL DISCLAIMER www.tiengineer.com *
; * ------------------ *
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; * all other warranties, express or implied, including, but not limited to, *
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; * purpose. Under no circumstances shall Texas Instruments be liable for *
; * any incidental, special or consequential damages that result from the *
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;\****************************************************************************/
;This test checks the MPY,MPYH and MPYHL instructions
.ref _Inst_Test ;system initialization section
.ref main_shell ;the main control shell that calls
;all the subroutines
.def mult
.sect "multchk"
;ARGUMENTS PASSED TO THIS ROUTINE
;A4 = 0FFFFh
;B4 = 5454h
;A6 = 5151h
;B6 = 3333h
;A8 = AAAAh
;B8 = 2222h
;A10 = FFFFFFFFh
;B10 = 00000003h
mult:
;saving (or pushing) appropriate registers onto the stack
STW .D2 A10, *B15--[1] ;decrementing SP
STW .D2 B10, *B15--[1] ;coping variables
STW .D2 B11, *B15--[1] ;A0-A9, B0-B9 are
STW .D2 B12, *B15--[1] ;saved by the
STW .D2 B13, *B15--[1] ;calling function
;checking multiply instructions
MPY .M2 B10, A10, B12 ;B12 = FFFFFFFDh
NOP
NEG .L2 B12, B12 ;B12 = 00000003h
CMPEQ .L2 B12, B10, B1 ;B1 = 1, if B12 = B10
SUB .L2 B1, 1, B1 ;B1 = 0
[B1] B .S2 ERRMULT1 ;ERROR, if B1 != 0
NOP 5
;B10 is treated as unsigned while A10 is signed. Therefore, it
;gives the same result
MPYUS .M2 B10, A10, B11 ;B10 is unsigned
NOP ;A10 is signed
NEG .L2 B11, B11 ;same result as prev.
SUB .L2 B11, B10, B2 ;B2 = 0, if B11 = B10
[B2] B .S2 ERRMULT1 ;ERROR, if B2 != 0
NOP 5
MVKL .S2 0002FFFDh, B13 ;EXPECTED RESULT
MVKH .S2 0002FFFDh, B13 ;B13 = 0002FFFDh
MPYSU .M2 B10, A10, B11 ;B11 = 0002fffdh
MPYU .M2 B10, A10, B12 ;B12 = 0002fffdh
NOP
CMPEQ .L2 B11, B12, B0 ;B0 = 1, if B11 = B12
SUB .L2 B0, 1, B0 ;B0 = 0
[!B0] CMPEQ .L2 B12, B13, B0 ;B0 = 1, if B12 = B13
SUB .L2 B0, 1, B0 ;B0 = 0
[B0] B .S2 ERRMULT1 ;ERROR, if B0 != 0
NOP 5
;checking for MPYH instructions
;preliminary setup
MVKL .S2 00230000h, B5 ;B5 = 35
MVKH .S2 00230000h, B5
MVKL .S1 0FFA71234h, A5 ;A5 = 89
MVKH .S1 0FFA71234h, A5
MVKL .S2 0FFFFF3D5h, B1 ;B1 = -3115
MVKH .S2 0FFFFF3D5h, B1
MVKL .S2 0022F3D5h, B2 ;B2 = 2290645
MVKH .S2 0022F3D5h, B2
;checking the instruction
MPYH .M2 B5, A5, B7 ;B7 = FFFFF3D5h
MPYHU .M2 B5, A5, B9 ;B9 = 0022F3D5h
MPYHUS .M2 B5, A5, B11 ;B5 = FFFFF3D5h
MPYHSU .M2 B5, A5, B12 ;B12 = 0022F3D5h
; NOP ;saving a cycle
CMPEQ .L2 B7, B11, B0 ;if B7 = B11, B0 = 1
SUB .L2 B0, 1, B0 ;B0 = 0
[!B0] CMPEQ .L2 B9, B12, B0 ;B0 = 1, if B9 = B12
SUB .L2 B0, 1, B0 ;B0 = 0
[!B0] CMPEQ .L2 B7, B1, B0 ;B0 = 1, if B7 = B1
SUB .L2 B0, 1, B0 ;B0 = 0
[B0] B .S2 ERRMULT2 ;ERROR, if B0 != 0
NOP 5
MPYHTEST: CMPEQ .L2 B9, B2, B0 ;B0 = 1, if B9 = B2
SUB .L2 B0, 1, B0 ;B0 = 0
[B0] B .S2 ERRMULT3 ;ERROR, if B0 != 0
NOP 5
;************************************************
;* This segment of the routine checks for MPYHL *
;* and MPYLH instructions. *
;************************************************
MPY .M2x A4, B4, B2 ;B2 = FFFFABACh
MPYHL .M1x A4, B4, A2 ;A2 = 00000000h
NOP
CMPLT .L2x B2, A2, B2 ;if B2 > A2, B2 = 1
SUB .L2 B2, 1, B2 ;B2 = 0
[B2] B .S2 ERRMULT4 ;ERROR, if A2 !=0
NOP 5
;********************************************************
;A4 = 0000 FFFFh *
;B4 = 0000 5454h *
;MPY = FFFFABACh (16lsb x 16lsb) *
;MPYHL = 0000 (A4 16msb) x 5454 (B4 16lsb) = 00000000 *
;MPYLH = FFFF (A4 16lsb) x 0000 (B4 16msb) = 00000000 *
;********************************************************
MPYLH .M2x A4, B4, B2 ;B2 = 00000000h
NOP
CMPEQ .L1x B2, A2, A2 ;A2 = 1, if A2 = B2
SUB .L1 A2, 1, A2 ;A2 = 0
[A2] B .S2 ERRMULT5
NOP 5
;*************************************************************************
;Code for instruction-set exteded for C64x support *
;checking for instruction ABS2 *
;*************************************************************************
;checking instruction AVG2
;Average, Signed Packed 16-bit
MVKL .S2 0x61984357, B16 ;B16 = src1
MVKH .S2 0x61984357, B16 ;B16 = src1
MVKL .S2 0x7582AE15, B18 ;B18 = src2
MVKH .S2 0x7582AE15, B18 ;B18 = src2
MVKL .S2 0x6B8DF8B6, B19 ;B19 = result
MVKH .S2 0x6B8DF8B6, B19 ;B19 = result
AVG2 .M2 B16, B18, B20
NOP 2 ;Delay Slot
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT6 ;ERROR, if B0 !=0
NOP 5
;checking instruction AVGU4
;Average, Signed Packed 8-bit
MVKL .S2 0x1A2E5F4E, B16 ;B16 = src1
MVKH .S2 0x1A2E5F4E, B16 ;B16 = src1
MVKL .S2 0x9EF26E3F, B18 ;B18 = src2
MVKH .S2 0x9EF26E3F, B18 ;B18 = src2
MVKL .S2 0x5C906747, B19 ;B19 = result
MVKH .S2 0x5C906747, B19 ;B19 = result
AVGU4 .M2 B16, B18, B20
NOP 2 ;Delay Slot
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT7 ;ERROR, if B0 !=0
NOP 5
;checking instruction BITC4
;Bit count, Packed 8-bit
MVKL .S2 0x9E526E30, B18 ;B18 = src2
MVKH .S2 0x9E526E30, B18 ;B18 = src2
MVKL .S2 0x05030502, B19 ;B19 = result
MVKH .S2 0x05030502, B19 ;B19 = result
BITC4 .M2 B18, B20
NOP 2 ;Delay Slot
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT8 ;ERROR, if B0 !=0
NOP 5
;checking instruction BITR
;Bit Reverse
MVKL .S2 0xA6E2C179, B18 ;B18 = src2
MVKH .S2 0xA6E2C179, B18 ;B18 = src2
MVKL .S2 0x9E834765, B19 ;B19 = result
MVKH .S2 0x9E834765, B19 ;B19 = result
BITR .M2 B18, B20
NOP 2 ;Delay Slot
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT9 ;ERROR, if B0 !=0
NOP 5
;checking instruction DEAL
;De-Interleave and pack
MVKL .S2 0x9E526E30, B18 ;B18 = src2
MVKH .S2 0x9E526E30, B18 ;B18 = src2
MVKL .S2 0xB1746CA4, B19 ;B19 = result
MVKH .S2 0xB1746CA4, B19 ;B19 = result
DEAL .M2 B18, B20
NOP 2 ;Delay Slot
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT10 ;ERROR, if B0 !=0
NOP 5
;checking instruction DOTP2
;Dot Product, Signed Packed 16-bit
MVKL .S2 0x6A321193, B16 ;B16 = src1
MVKH .S2 0x6A321193, B16 ;B16 = src1
MVKL .S2 0xB1746CA4, B18 ;B18 = src2
MVKH .S2 0xB1746CA4, B18 ;B18 = src2
MVKL .S2 0xE6DFF6D4, B19 ;B19 = result
MVKH .S2 0xE6DFF6D4, B19 ;B19 = result
DOTP2 .M2 B16, B18, B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT11 ;ERROR, if B0 !=0
NOP 5
;checking instruction DOTPN2
;Dot product with negate, signed packed 16-bit
MVKL .S2 0x3629274A, B16 ;B16 = src1
MVKH .S2 0x3629274A, B16 ;B16 = src1
MVKL .S2 0x325C8036, B18 ;B18 = src2
MVKH .S2 0x325C8036, B18 ;B18 = src2
MVKL .S2 0x1E442F20, B19 ;B19 = result
MVKH .S2 0x1E442F20, B19 ;B19 = result
DOTPN2 .M2 B16, B18, B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT12 ;ERROR, if B0 !=0
NOP 5
;checking instruction DOTPNRSU2
;Dot Product with negate, shift and round, signed by unsigned packed 16-bit
MVKL .S2 0xFFFFF6FA, B19 ;B19 = result
MVKH .S2 0xFFFFF6FA, B19 ;B19 = result
DOTPNRSU2 .M2 B16, B18, B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT13 ;ERROR, if B0 !=0
NOP 5
;checking instruction DOTPNRUS2
;Dot Product with negate, shift and round, unsigned by signed packed 16-bit
;(Pseudo-Operation)
MVKL .S2 0x00001E44, B19 ;B19 = result
MVKH .S2 0x00001E44, B19 ;B19 = result
DOTPNRUS2 .M2 B16, B18, B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT14 ;ERROR, if B0 !=0
NOP 5
;checking instruction DOTPRSU2
;Dot Product with shift and round, signed by unsigned packed 16-bit
MVKL .S2 0x00001E55, B19 ;B19 = result
MVKH .S2 0x00001E55, B19 ;B19 = result
DOTPRSU2 .M2 B16, B18, B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT15 ;ERROR, if B0 !=0
NOP 5
;checking instruction DOTPRUS2
;Dot Product with shift and round, signed by unsigned packed 16-bit
MVKL .S2 0xFFFFF70B, B19 ;B19 = result
MVKH .S2 0xFFFFF70B, B19 ;B19 = result
DOTPRUS2 .M2 B16, B18, B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT16 ;ERROR, if B0 !=0
NOP 5
;checking instruction DOTPSU4
;Dot Product, Signed by Unsigned Packed 8-Bit
MVKL .S2 0x6A321193, B16 ;B16 = src1
MVKH .S2 0x6A321193, B16 ;B16 = src1
MVKL .S2 0xB1746CA4, B18 ;B18 = src2
MVKH .S2 0xB1746CA4, B18 ;B18 = src2
MVKL .S2 0x0000214A, B19 ;B19 = result
MVKH .S2 0x0000214A, B19 ;B19 = result
DOTPSU4 .M2 B16, B18, B20
NOP 4 ;Delay Slot
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRMULT17 ;ERROR, if B0 !=0
NOP 5
;checking instruction DOTPUS4
;Dot Product, Signed by Unsigned Packed 8-Bit
MVKL .S2 0xFFFFC84A, B19 ;B19 = result
MVKH .S2 0xFFFFC84A, B19 ;B19 = result
DOTPUS4 .M2 B16, B18, B20
NOP 4 ;Delay Slot
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