📄 bbu_dd_emifacsl.h
字号:
been latched) */
#define EMIFA_CESEC_CEEXT_ACTIVE 0x00000001u /* On read cycles, the CE signal will
go active when SOE goes active and
will stay active until SOE goes inactive.
used for synchronous FIFO reads */
#define EMIFA_CESEC_SYNCWL_MASK 0x0000000Cu
#define EMIFA_CESEC_SYNCWL_SHIFT 0x00000002u
#define EMIFA_CESEC_SYNCWL_DEFAULT 0x00000000u
#define EMIFA_CESEC_SYNCWL_0CYCLE 0x00000000u /* 0 cycle write latency */
#define EMIFA_CESEC_SYNCWL_1CYCLE 0x00000001u /* 1 cycle write latency */
#define EMIFA_CESEC_SYNCWL_2CYCLE 0x00000002u /* 2 cycle write latency */
#define EMIFA_CESEC_SYNCWL_3CYCLE 0x00000003u /* 3 cycle write latency */
#define EMIFA_CESEC_SYNCRL_MASK 0x00000003u
#define EMIFA_CESEC_SYNCRL_SHIFT 0x00000000u
#define EMIFA_CESEC_SYNCRL_DEFAULT 0x00000002u
#define EMIFA_CESEC_SYNCRL_0CYCLE 0x00000000u /* 0 cycle read latency */
#define EMIFA_CESEC_SYNCRL_1CYCLE 0x00000001u /* 1 cycle read latency */
#define EMIFA_CESEC_SYNCRL_2CYCLE 0x00000002u /* 2 cycle read latency */
#define EMIFA_CESEC_SYNCRL_3CYCLE 0x00000003u /* 3 cycle read latency */
/******************************************************************************\
* EMIFA Registers Macro Definitions
*
* ASDCTL - EMIFA SDRAM control regsiter
*
* SDBSZ[30] - rw, SDRAM bank size bit
* SDRSZ[29:28] - rw, SDRAM row size bits
* SDCSZ[27:26] - rw, SDRAM column size bits
* RFEN[25] - rw, Refresh enable bit. If SDRAM is not used, be sure RFEN = 0;
* otherwise, BUSREQ may become asserted when SDRAM timer
* counts down to 0
* INIT[24] - w, Initialization bit. This bit forces initialization of all
* SDRAM present. Reading this bit returns an undefined value.
* EMIFA automatically changes INIT back to 0 after SDRAM
* initialization is performed
* TRCD[23:20] - rw, Specifies the tRCD value of the SDRAM in EMIFA clock cycles
* TRP[19:16] - rw, Specifies the tRP value of the SDRAM in EMIFA clock cycles* TRC[15:12] - rw, Specifies the tRC value of the SDRAM in EMIFA clock cycles* SLFRFR[0] - rw, Self-refresh mode bit
*
\******************************************************************************/
#define EMIFA_SDCTL_OFFSET 6
#define EMIFA_SDCTL_ADDR 0x01800018u
#define EMIFA_SDCTL_DEFAULT 0x0248F000u
#define EMIFA_SDCTL_SDBSZ_MASK 0x40000000u
#define EMIFA_SDCTL_SDBSZ_SHIFT 0x0000001Eu
#define EMIFA_SDCTL_SDBSZ_DEFAULT 0x00000000u
#define EMIFA_SDCTL_SDBSZ_2BANKS 0x00000000u /* one bank select pin (two banks)*/
#define EMIFA_SDCTL_SDBSZ_4BANKS 0x00000001u /* two bank select pin (four banks)*/
#define EMIFA_SDCTL_SDRSZ_MASK 0x30000000u
#define EMIFA_SDCTL_SDRSZ_SHIFT 0x0000001Cu
#define EMIFA_SDCTL_SDRSZ_DEFAULT 0x00000000u
#define EMIFA_SDCTL_SDRSZ_11ROW 0x00000000u /* 11 row address pins (2048 rows per bank)*/
#define EMIFA_SDCTL_SDRSZ_12ROW 0x00000001u /* 12 row address pins (4096 rows per bank)*/
#define EMIFA_SDCTL_SDRSZ_13ROW 0x00000002u /* 13 row address pins (8192 rows per bank)*/
#define EMIFA_SDCTL_SDCSZ_MASK 0x0C000000u
#define EMIFA_SDCTL_SDCSZ_SHIFT 0x0000001Au
#define EMIFA_SDCTL_SDCSZ_DEFAULT 0x00000000u
#define EMIFA_SDCTL_SDCSZ_9COL 0x00000000u /* 9 column address pins (512 elements per row) */
#define EMIFA_SDCTL_SDCSZ_8COL 0x00000001u /* 8 column address pins (256 elements per row) */
#define EMIFA_SDCTL_SDCSZ_10COL 0x00000002u /* 10 column address pins (1024 elements per row)*/
#define EMIFA_SDCTL_RFEN_MASK 0x02000000u
#define EMIFA_SDCTL_RFEN_SHIFT 0x00000019u
#define EMIFA_SDCTL_RFEN_DEFAULT 0x00000001u
#define EMIFA_SDCTL_RFEN_DISABLE 0x00000000u /* SDRAM refresh disabled */
#define EMIFA_SDCTL_RFEN_ENABLE 0x00000001u /* SDRAM refresh enabled */
#define EMIFA_SDCTL_INIT_MASK 0x01000000u
#define EMIFA_SDCTL_INIT_SHIFT 0x00000018u
#define EMIFA_SDCTL_INIT_DEFAULT 0x00000001u
#define EMIFA_SDCTL_INIT_NO 0x00000000u /* no effect */
#define EMIFA_SDCTL_INIT_YES 0x00000001u /* initialize SDRAM in each
CE space configured for SDRAM */
#define EMIFA_SDCTL_TRCD_MASK 0x00F00000u
#define EMIFA_SDCTL_TRCD_SHIFT 0x00000014u
#define EMIFA_SDCTL_TRCD_DEFAULT 0x00000004u
#define EMIFA_SDCTL_TRP_MASK 0x000F0000u
#define EMIFA_SDCTL_TRP_SHIFT 0x00000010u
#define EMIFA_SDCTL_TRP_DEFAULT 0x00000008u
#define EMIFA_SDCTL_TRC_MASK 0x0000F000u
#define EMIFA_SDCTL_TRC_SHIFT 0x0000000Cu
#define EMIFA_SDCTL_TRC_DEFAULT 0x0000000Fu
#define EMIFA_SDCTL_SLFRFR_MASK 0x00000001u
#define EMIFA_SDCTL_SLFRFR_SHIFT 0x00000000u
#define EMIFA_SDCTL_SLFRFR_DEFAUL 0x00000000u
#define EMIFA_SDCTL_SLFRFR_DISABL 0x00000000u /* self-refresh mode disabled */
#define EMIFA_SDCTL_SLFRFR_ENABLE 0x00000001u /* self-refresh mode enabled */
/******************************************************************************\
* EMIFA Registers Macro Definitions
*
* ASDTIM - EMIFA SDRAM timing register
*
* XRFR[25:24] - rw, Extra refreshes controls the number of refreshes performed
* to SDRAM when the refresh counter expires
* CNTR[23:12] - r, Current value of the refresh counter
* PERIOD[11:0] - rw, Refresh period in EMIFA clock cycle
*
\******************************************************************************/
#define EMIFA_SDTIM_OFFSET 7
#define EMIFA_SDTIM_ADDR 0x0180001Cu
#define EMIFA_SDTIM_DEFAULT 0x005DC5DCu
#define EMIFA_SDTIM_XRFR_MASK 0x03000000u
#define EMIFA_SDTIM_XRFR_SHIFT 0x00000018u
#define EMIFA_SDTIM_XRFR_DEFAULT 0x00000000u
#define EMIFA_SDTIM_CNTR_MASK 0x00FFF000u
#define EMIFA_SDTIM_CNTR_SHIFT 0x0000000Cu
#define EMIFA_SDTIM_CNTR_DEFAULT 0x000005DCu
#define EMIFA_SDTIM_PERIOD_MASK 0x00000FFFu
#define EMIFA_SDTIM_PERIOD_SHIFT 0x00000000u
#define EMIFA_SDTIM_PERIOD_DEFAULT 0x000005DCu
/******************************************************************************\
* EMIFA Registers Macro Definitions
*
* ASDEXT - EMIFA SDRAM extension register
*
* WR2RD[20] - rw, Specifies minimum number of cycles between WRITE to READ
* command of the SDRAM in AECLKOUT1 cycles
* WR2RD = (# of cycles WRITE to READ) - 1
* WR2DEAC[19:18] - rw, Specifies minimum number of cycles between WRITE to
* DEAC/DCAB command of the SDRAM in AECLKOUT1 cycles
* WR2DEAC = (# of cycles WRITE to DEAC/DCAB) - 1
* WR2WR[17] - rw, Specifies minimum number of cycles between WRITE to WRITE
* command of the SDRAM in AECLKOUT1 cycles
* WR2WR = (# of cycles WRITE to WRITE) - 1
* R2WDQM[16:15] - rw, Specifies number of of cycles that BEx signals must be
* high preceding a WRITE interrupting a READ
* R2WDQM = (# of cycles BEx high) - 1
* RD2WR[14:12] - rw, Specifies number of cycles between READ to WRITE command
* of the SDRAM in AECLKOUT1 cycles
* RD2WR = (# of cycles READ to WRITE) - 1
* RD2DEAC[11:10] - rw, Specifies number of cycles between READ to DEAC/DCAB of
* the SDRAM in AECLKOUT1 cycles
* RD2DEAC = (# of cycles READ to DEAC/DCAB) - 1
* RD2RD[9] - rw, Specifies number of cycles between READ to READ command
* (same CE space) of the SDRAM in AECLKOUT1 cycles
* RD2RD = (# of cycles READ to READ) - 1
* THZP[8:7] - rw, Specifies tHZP (also known as tROH) value of the SDRAM
* in AECLKOUT1 cycles
* THZP = tHZP / tcyc - 1* TWR[6:5] - rw, Specifies tWR value of the SDRAM in AECLKOUT1 cycles
* TWR = tWR / tcyc - 1
* TRRD[4] - rw, Specifies tRRD value of the SDRAM in AECLKOUT1 cycles
* 0: TRRD = 2 AECLKOUT1 cycles
* 1: TRRD = 3 AECLKOUT1 cycles
* TRAS[3:1] - rw, Specifies tRAS value of the SDRAM in AECLKOUT1 cycles
* TRAS = tRAS / tcyc - 1
* TCL[0] - rw, Specified CAS latency of the SDRAM in AECLKOUT1 cycles
* 0: CAS latency = 2 AECLKOUT1 cycles
* 1: CAS latency = 3 AECLKOUT1 cycles
*
\******************************************************************************/
#define EMIFA_SDEXT_OFFSET 8
#define EMIFA_SDEXT_ADDR 0x01800020u
#define EMIFA_SDEXT_DEFAULT 0x00175F3Fu
#define EMIFA_SDEXT_WR2RD_MASK 0x00100000u
#define EMIFA_SDEXT_WR2RD_SHIFT 0x00000014u
#define EMIFA_SDEXT_WR2RD_DEFAULT 0x00000001u
#define EMIFA_SDEXT_WR2DEAC_MASK 0x000C0000u
#define EMIFA_SDEXT_WR2DEAC_SHIFT 0x00000012u
#define EMIFA_SDEXT_WR2DEAC_DEFAULT 0x00000001u
#define EMIFA_SDEXT_WR2WR_MASK 0x00020000u
#define EMIFA_SDEXT_WR2WR_SHIFT 0x00000011u
#define EMIFA_SDEXT_WR2WR_DEFAULT 0x00000001u
#define EMIFA_SDEXT_R2WDQM_MASK 0x00018000u
#define EMIFA_SDEXT_R2WDQM_SHIFT 0x0000000Fu
#define EMIFA_SDEXT_R2WDQM_DEFAULT 0x00000002u
#define EMIFA_SDEXT_RD2WR_MASK 0x00007000u
#define EMIFA_SDEXT_RD2WR_SHIFT 0x0000000Cu
#define EMIFA_SDEXT_RD2WR_DEFAULT 0x00000005u
#define EMIFA_SDEXT_RD2DEAC_MASK 0x00000C00u
#define EMIFA_SDEXT_RD2DEAC_SHIFT 0x0000000Au
#define EMIFA_SDEXT_RD2DEAC_DEFAULT 0x00000003u
#define EMIFA_SDEXT_RD2RD_MASK 0x00000200u
#define EMIFA_SDEXT_RD2RD_SHIFT 0x00000009u
#define EMIFA_SDEXT_RD2RD_DEFAULT 0x00000001u
#define EMIFA_SDEXT_THZP_MASK 0x00000180u
#define EMIFA_SDEXT_THZP_SHIFT 0x00000007u
#define EMIFA_SDEXT_THZP_DEFAULT 0x00000002u
#define EMIFA_SDEXT_TWR_MASK 0x00000060u
#define EMIFA_SDEXT_TWR_SHIFT 0x00000005u
#define EMIFA_SDEXT_TWR_DEFAULT 0x00000001u
#define EMIFA_SDEXT_TRRD_MASK 0x00000010u
#define EMIFA_SDEXT_TRRD_SHIFT 0x00000004u
#define EMIFA_SDEXT_TRRD_DEFAULT 0x00000001u
#define EMIFA_SDEXT_TRAS_MASK 0x0000000Eu
#define EMIFA_SDEXT_TRAS_SHIFT 0x00000001u
#define EMIFA_SDEXT_TRAS_DEFAULT 0x00000007u
#define EMIFA_SDEXT_TCL_MASK 0x00000001u
#define EMIFA_SDEXT_TCL_SHIFT 0x00000000u
#define EMIFA_SDEXT_TCL_DEFAULT 0x00000001u
/*----------------------------------------------------------------------------*/
/******************************************************************************\
* EMIFA Raw Registers Access Macro Definitions
\******************************************************************************/
#define EMIFA_RSET(REG,x) (*(volatile Uint32*)(EMIFA_##REG##_ADDR))=((Uint32)(x))
#define EMIFA_RGET(REG) (Uint32)(*(volatile Uint32*)(EMIFA_##REG##_ADDR))
#define EMIFA_FSET(N,REG,FIELD,x) EMIFA_RSET(##REG##N, (EMIFA_RGET(##REG##N) & ~EMIFA_##REG##_##FIELD##_MASK) \
| (((Uint32)(x) << EMIFA_##REG##_##FIELD##_SHIFT) & EMIFA_##REG##_##FIELD##_MASK))
#define EMIFA_FGET(N,REG,FIELD) (Uint32)((((Uint32)(*(volatile Uint32*)(EMIFA_##REG##N##_ADDR))) \
& EMIFA_##REG##_##FIELD##_MASK) >> EMIFA_##REG##_##FIELD##_SHIFT)
/*----------------------------------------------------------------------------*/
/******************************************************************************\
* EMIFA Global Typedef Declarations
\******************************************************************************/
/* EMIFA Configuration Structure */
typedef struct {
Uint32 gblctl;
Uint32 cectl0;
Uint32 cectl1;
Uint32 cectl2;
Uint32 cectl3;
Uint32 cesec0;
Uint32 cesec1;
Uint32 cesec2;
Uint32 cesec3;
Uint32 sdctl;
Uint32 sdtim;
Uint32 sdext;
} EMIFA_Config;
/*----------------------------------------------------------------------------*/
/******************************************************************************\
* EDMA Global Typedef Declarations for EMIFA
\******************************************************************************/
typedef struct
{
EDMA_Handle hCEdma1;
EDMA_Handle hCEdma2;
Uint32 sour0Add;
Uint32 dest0Add;
Uint32 eleCount0;
Uint32 sour1Add;
Uint32 dest1Add;
Uint32 eleCount1;
Uint32 sour2Add;
Uint32 dest2Add;
Uint32 eleCount2;
Uint32 priority;
Sint32 chainStage;
} EDMA_DpramConfig;
typedef struct
{
Uint32 sourAdd;
Uint32 destAdd;
Uint32 eleCount;
Uint32 priority;
} EDMA_SdramConfig;
/*----------------------------------------------------------------------------*/
#endif /*_BBU_DD_EMIFACSL_H_ */
/******************************************************************************\
* End of BBU_DD_EmifaCsl.h
\******************************************************************************/
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -