bbu_dd_emifacsl.h

DSP芯片自检测程序

/*******************************************************************************
* COPYRIGHT (C)             中国普天研究院									   *
********************************************************************************
* 源文件名: BBU_DD_EmifaCsl.h                                                  *
* 功能描述：Registers Description for EMIFA in TMS320C6414 and TMS320C6416     *
* 编写者：louyj                                                                *
* 版本：1.0.0                                                                  *
* 编制日期：07/27/2004                                                         *
* 说明：                                                                       *
* 修改历史：                                                                   *
*                                                                              *
*******************************************************************************/

/*------------------------------------------------------------------------------
* Registers Descriptions for EMIFA in TMS320C6414 and TMS320C6416
*
* AGBLCTL  - EMIFA global control register
*
* ACECTL0  - EMIFA CE0 space control register
* ACECTL1  - EMIFA CE1 space control register
* ACECTL2  - EMIFA CE2 space control register
* ACECTL3  - EMIFA CE3 space control register
*
* ACESEC0  - EMIFA CE0 space secondary control register
* ACESEC1  - EMIFA CE1 space secondary control register
* ACESEC2  - EMIFA CE2 space secondary control register
* ACESEC3  - EMIFA CE3 space secondary control register
*
* ASDCTL   - EMIFA SDRAM control regsiter
* ASDTIM   - EMIFA SDRAM timing register
* ASDEXT   - EMIFA SDRAM extension register
*
\******************************************************************************/
#ifndef _BBU_DD_EMIFACSL_H_
#define _BBU_DD_EMIFACSL_H_

#include "BBU_DD_Stdinc.h"
#include "BBU_DD_EdmaCsl.h"

/******************************************************************************\
* EMIFA Global Macro Definitions
\******************************************************************************/  
#define EMIFA_BASE_GLOBAL               0x01800000u

/******************************************************************************\
*                 EMIFA Registers Macro Definitions
* 
* AGBLCTL - EMIFA global control register
*
* EK2RATE[19:18]     - rw, ECLKOUT2 rate
* EK2HZ[17]          - rw, ECLKOUT2 high-impedance control bit
* EK2EN[16]          - rw, ECLKOUT2 enable bit
* BRMODE[13]         - rw, BRMODE indicates if BUSREQ shows memory refresh status 
* BUSREQ[11]         - r,  if EMIFA has an access/refresh pending or in progress
* ARDY[10]           - r,  ARDY input bit (when async CEn is active)
* HOLD[9]            - r,  HOLD input bit
* HOLDA[8]           - r,  HOLDA output bit
* NOHOLD[7]          - rw, External NOHOLD enable bit
* EK1HZ[6]           - rw, ECLKOUT1 high-impedance control bit
* EK1EN[5]           - rw, ECLKOUT1 enable bit
* CLK4EN[4]          - rw, CLKOUT4 enable bit
* CLK6EN[3]          - rw, CLKOUT6 enable bit
*
\******************************************************************************/
#define EMIFA_GBLCTL_OFFSET             0
#define EMIFA_GBLCTL_ADDR               0x01800000u
#define EMIFA_GBLCTL_DEFAULT            0x00092078u

#define EMIFA_GBLCTL_EK2RATE_MASK       0x000C0000u
#define EMIFA_GBLCTL_EK2RATE_SHIFT      0x00000012u
#define EMIFA_GBLCTL_EK2RATE_DEFAULT    0x00000002u
#define EMIFA_GBLCTL_EK2RATE_FULLCLK    0x00000000u /* 1× EMIFA input clock rate */
#define EMIFA_GBLCTL_EK2RATE_HALFCLK    0x00000001u /* 1/2× EMIFA input clock rate */
#define EMIFA_GBLCTL_EK2RATE_QUARCLK    0x00000002u /* 1/4× EMIFA input clock rate */

#define EMIFA_GBLCTL_EK2HZ_MASK         0x00020000u
#define EMIFA_GBLCTL_EK2HZ_SHIFT        0x00000011u
#define EMIFA_GBLCTL_EK2HZ_DEFAULT      0x00000000u
#define EMIFA_GBLCTL_EK2HZ_CLK          0x00000000u /* AECLKOUT2 continues 
                                                       clocking during Hold */
#define EMIFA_GBLCTL_EK2HZ_HIGHZ        0x00000001u /* AECLKOUT2 is in HighZ
                                                       state during Hold */

#define EMIFA_GBLCTL_EK2EN_MASK         0x00010000u
#define EMIFA_GBLCTL_EK2EN_SHIFT        0x00000010u
#define EMIFA_GBLCTL_EK2EN_DEFAULT      0x00000001u
#define EMIFA_GBLCTL_EK2EN_DISABLE      0x00000000u /* AECLKOUT2 is held low */
#define EMIFA_GBLCTL_EK2EN_ENABLE       0x00000001u /* AECLKOUT2 is enabled to
                                                       clock */ 

#define EMIFA_GBLCTL_BRMODE_MASK        0x00002000u
#define EMIFA_GBLCTL_BRMODE_SHIFT       0x0000000Du
#define EMIFA_GBLCTL_BRMODE_DEFAULT     0x00000001u
#define EMIFA_GBLCTL_BRMODE_MSTATUS     0x00000000u /* BUSREQ indicates memory access
                                                       pending or in progress */
#define EMIFA_GBLCTL_BRMODE_MRSTATUS    0x00000001u /* BUSREQ indicates memory access
                                                       or refresh pending or in progress */

#define EMIFA_GBLCTL_BUSREQ_MASK        0x00000800u
#define EMIFA_GBLCTL_BUSREQ_SHIFT       0x0000000Bu
#define EMIFA_GBLCTL_BUSREQ_DEFAULT     0x00000000u
#define EMIFA_GBLCTL_BUSREQ_LOW         0x00000000u /* BUSREQ output is low. 
                                                       No access/refresh pending */
#define EMIFA_GBLCTL_BUSREQ_HIGH        0x00000001u /* BUSREQ output is high.
                                                       Access/refresh pending or in progress */

#define EMIFA_GBLCTL_ARDY_MASK          0x00000400u
#define EMIFA_GBLCTL_ARDY_SHIFT         0x0000000Au
#define EMIFA_GBLCTL_ARDY_DEFAULT       0x00000000u
#define EMIFA_GBLCTL_ARDY_LOW           0x00000000u /* ARDY input is low. 
                                                       External device is not ready */
#define EMIFA_GBLCTL_ARDY_HIGH          0x00000001u /* ARDY input is high.
                                                       External device is ready */

#define EMIFA_GBLCTL_HOLD_MASK          0x00000200u
#define EMIFA_GBLCTL_HOLD_SHIFT         0x00000009u
#define EMIFA_GBLCTL_HOLD_DEFAULT       0x00000000u
#define EMIFA_GBLCTL_HOLD_LOW           0x00000000u /* HOLD input is low.
                                                       External device requesting EMIFA */
#define EMIFA_GBLCTL_HOLD_HIGH          0x00000001u /* HOLD input is high.
                                                       No external request pending */

#define EMIFA_GBLCTL_HOLDA_MASK         0x00000100u
#define EMIFA_GBLCTL_HOLDA_SHIFT        0x00000008u
#define EMIFA_GBLCTL_HOLDA_DEFAULT      0x00000000u
#define EMIFA_GBLCTL_HOLDA_LOW          0x00000000u /* HOLDA output is low.
                                                       External device owns EMIFA */
#define EMIFA_GBLCTL_HOLDA_HIGH         0x00000001u /* HOLDA output is high.
                                                       External device does not own EMIFA */

#define EMIFA_GBLCTL_NOHOLD_MASK        0x00000080u
#define EMIFA_GBLCTL_NOHOLD_SHIFT       0x00000007u
#define EMIFA_GBLCTL_NOHOLD_DEFAULT     0x00000000u
#define EMIFA_GBLCTL_NOHOLD_DISABLE     0x00000000u /* No hold is disabled.
                                                       Hold requests via the HOLD input are
                                                       acknowledged via the HOLDA output
                                                       at the earliest possible time */
#define EMIFA_GBLCTL_NOHOLD_ENABLE      0x00000001u /* No hold is enabled.
                                                       Hold requests via the HOLD input are
                                                       ignored */

#define EMIFA_GBLCTL_EK1HZ_MASK         0x00000040u
#define EMIFA_GBLCTL_EK1HZ_SHIFT        0x00000006u
#define EMIFA_GBLCTL_EK1HZ_DEFAULT      0x00000001u
#define EMIFA_GBLCTL_EK1HZ_CLK          0x00000000u /* AECLKOUT1 continues
                                                       clocking during Hold */
#define EMIFA_GBLCTL_EK1HZ_HIGHZ        0x00000001u /* AECLKOUT1 is in HighZ
                                                       state during Hold */ 

#define EMIFA_GBLCTL_EK1EN_MASK         0x00000020u
#define EMIFA_GBLCTL_EK1EN_SHIFT        0x00000005u
#define EMIFA_GBLCTL_EK1EN_DEFAULT      0x00000001u
#define EMIFA_GBLCTL_EK1EN_DISABLE      0x00000000u /* AECLKOUT1 is held low */  
#define EMIFA_GBLCTL_EK1EN_ENABLE       0x00000001u /* AECLKOUT1 is enabled to   
                                                       clock */                 
#define EMIFA_GBLCTL_CLK4EN_MASK        0x00000010u
#define EMIFA_GBLCTL_CLK4EN_SHIFT       0x00000004u
#define EMIFA_GBLCTL_CLK4EN_DEFAULT     0x00000001u
#define EMIFA_GBLCTL_CLK4EN_DISABLE     0x00000000u /* CLKOUT4 is held high */
#define EMIFA_GBLCTL_CLK4EN_ENABLE      0x00000001u /* CLKOUT4 is enabled to clock */

#define EMIFA_GBLCTL_CLK6EN_MASK        0x00000008u
#define EMIFA_GBLCTL_CLK6EN_SHIFT       0x00000003u
#define EMIFA_GBLCTL_CLK6EN_DEFAULT     0x00000001u
#define EMIFA_GBLCTL_CLK6EN_DISABLE     0x00000000u /* CLKOUT6 is held high */          
#define EMIFA_GBLCTL_CLK6EN_ENABLE      0x00000001u /* CLKOUT6 is enabled to clock */   

/******************************************************************************\
*                 EMIFA Registers Macro Definitions
* 
* ACECTL0 - EMIFA CE0 space control register
* ACECTL1 - EMIFA CE1 space control register
* ACECTL2 - EMIFA CE2 space control register
* ACECTL3 - EMIFA CE3 space control register
*
* WRSETUP[31:28]     - rw, Write setup width
* WRSTRB[27:22]      - rw, Write strobe width
* WRHLD[21:20]       - rw, Write hold width
* RDSETUP[19:16]     - rw, Read setup width 
* TA[15:14]          - rw, Minimum Turn-Around time
* RDSTRB[13:8]       - rw, Read strobe width
* MTYPE[7:4]         - rw, Memory type of the corresponding CE spaces
* WRHLDMSB[3]        - rw, Write hold width MSB is the most-significant bit of write hold
* RDHLD[2:0]         - rw, Read hold width
*
\******************************************************************************/
#define EMIFA_CECTL0_OFFSET             2
#define EMIFA_CECTL1_OFFSET             1
#define EMIFA_CECTL2_OFFSET             4
#define EMIFA_CECTL3_OFFSET             5
#define EMIFA_CECTL0_ADDR               0x01800008u
#define EMIFA_CECTL1_ADDR               0x01800004u
#define EMIFA_CECTL2_ADDR               0x01800010u
#define EMIFA_CECTL3_ADDR               0x01800014u
#define EMIFA_CECTL_DEFAULT             0xFFFFFF03u

#define EMIFA_CECTL_WRSETUP_MASK        0xF0000000u
#define EMIFA_CECTL_WRSETUP_SHIFT       0x0000001Cu
#define EMIFA_CECTL_WRSETUP_DEFAULT     0x0000000Fu

#define EMIFA_CECTL_WRSTRB_MASK         0x0FC00000u
#define EMIFA_CECTL_WRSTRB_SHIFT        0x00000016u
#define EMIFA_CECTL_WRSTRB_DEFAULT      0x0000003Fu

#define EMIFA_CECTL_WRHLD_MASK          0x00300000u
#define EMIFA_CECTL_WRHLD_SHIFT         0x00000014u
#define EMIFA_CECTL_WRHLD_DEFAULT       0x00000003u

#define EMIFA_CECTL_RDSETUP_MASK        0x000F0000u
#define EMIFA_CECTL_RDSETUP_SHIFT       0x00000010u
#define EMIFA_CECTL_RDSETUP_DEFAULT     0x0000000Fu

#define EMIFA_CECTL_TA_MASK             0x0000C000u
#define EMIFA_CECTL_TA_SHIFT            0x0000000Eu
#define EMIFA_CECTL_TA_DEFAULT          0x00000003u

#define EMIFA_CECTL_RDSTRB_MASK         0x00003F00u
#define EMIFA_CECTL_RDSTRB_SHIFT        0x00000008u
#define EMIFA_CECTL_RDSTRB_DEFAULT      0x0000003Fu

#define EMIFA_CECTL_MTYPE_MASK          0x000000F0u
#define EMIFA_CECTL_MTYPE_SHIFT         0x00000004u
#define EMIFA_CECTL_MTYPE_DEFAULT       0x00000000u

#define EMIFA_CECTL_MTYPE_ASYNC8        0x00000000u
#define EMIFA_CECTL_MTYPE_ASYNC16       0x00000001u
#define EMIFA_CECTL_MTYPE_ASYNC32       0x00000002u
#define EMIFA_CECTL_MTYPE_SDRAM32       0x00000003u
#define EMIFA_CECTL_MTYPE_SYNC32        0x00000004u
#define EMIFA_CECTL_MTYPE_SDRAM8        0x00000008u
#define EMIFA_CECTL_MTYPE_SDRAM16       0x00000009u
#define EMIFA_CECTL_MTYPE_SYNC8         0x0000000Au
#define EMIFA_CECTL_MTYPE_SYNC16        0x0000000Bu
#define EMIFA_CECTL_MTYPE_ASYNC64       0x0000000Cu
#define EMIFA_CECTL_MTYPE_SDRAM64       0x0000000Du
#define EMIFA_CECTL_MTYPE_SYNC64        0x0000000Eu

#define EMIFA_CECTL_WRHLDMSB_MASK       0x00000008u
#define EMIFA_CECTL_WRHLDMSB_SHIFT      0x00000003u
#define EMIFA_CECTL_WRHLDMSB_DEFAULT    0x00000000u

#define EMIFA_CECTL_RDHLD_MASK          0x00000007u
#define EMIFA_CECTL_RDHLD_SHIFT         0x00000000u
#define EMIFA_CECTL_RDHLD_DEFAULT       0x00000003u

/******************************************************************************\
*                 EMIFA Registers Macro Definitions
* 
* ACESEC0 - EMIFA CE0 space secondary control register
* ACESEC1 - EMIFA CE1 space secondary control register
* ACESEC2 - EMIFA CE2 space secondary control register
* ACESEC3 - EMIFA CE3 space secondary control register
*
* SNCCLK[6]      - rw, Synchronization clock selection bit
* RENEN[5]       - rw, Read Enable enable bit
* CEEXT[4]       - rw, CE extension register ENABLE BIT
* SYNCWL[3:2]    - rw, Synchronous interface data write latency
* SYNCRL[1:0]    - rw, Synchronous interface data read latency 
*
\******************************************************************************/
#define EMIFA_CESEC0_OFFSET             18
#define EMIFA_CESEC1_OFFSET             17
#define EMIFA_CESEC2_OFFSET             20
#define EMIFA_CESEC3_OFFSET             21
#define EMIFA_CESEC0_ADDR               0x01800048u
#define EMIFA_CESEC1_ADDR               0x01800044u
#define EMIFA_CESEC2_ADDR               0x01800050u
#define EMIFA_CESEC3_ADDR               0x01800054u
#define EMIFA_CESEC_DEFAULT             0x00000002u 

#define EMIFA_CESEC_SNCCLK_MASK         0x00000040u
#define EMIFA_CESEC_SNCCLK_SHIFT        0x00000006u
#define EMIFA_CESEC_SNCCLK_DEFAULT      0x00000000u
#define EMIFA_CESEC_SNCCLK_ECLKOUT1     0x00000000u /* Control/data signals are 
                                                       synchronized to ECLKOUT1 */ 
#define EMIFA_CESEC_SNCCLK_ECLKOUT2     0x00000001u /* Control/data signals are 
                                                       synchronized to ECLKOUT2 */                                                   

#define EMIFA_CESEC_RENEN_MASK          0x00000020u
#define EMIFA_CESEC_RENEN_SHIFT         0x00000005u
#define EMIFA_CESEC_RENEN_DEFAULT       0x00000000u
#define EMIFA_CESEC_RENEN_ADS           0x00000000u /* ADS mode for SBSRAM or 
                                                       ZBT SRAM interface */
#define EMIFA_CESEC_RENEN_READ          0x00000001u /* Read enable mode for
                                                       FIFO interface */

#define EMIFA_CESEC_CEEXT_MASK          0x00000010u
#define EMIFA_CESEC_CEEXT_SHIFT         0x00000004u
#define EMIFA_CESEC_CEEXT_DEFAULT       0x00000000u
#define EMIFA_CESEC_CEEXT_INACTIVE      0x00000000u /* CE goes inactive after the final
                                                       command has been issued (not
                                                       necessarily when all the data has