bbu_dd_mcbspcsl.h

DSP芯片自检测程序

* FSXM[11]       - rw, Transmit frame-synchronization mode bit                                                  
* FSRM[10]       - rw, Receive frame-synchronization mode bit                                 
* CLKXM[9]       - rw, Transmitter clock mode bit                                     
* CLKRM[8]       - rw, Receiver clock mode bit                                                                                   
* CLKSSTAT[6]    - r,  Reflects value on CLKS pin when configured as a general
*                      purpose input pin                                                   
* DXSTAT[5]      - rw, Reflects value driven to DX pin when configured as a
*                      general purpose output pin                                                  
* DRSTAT[4]      - r,  Reflects value on DR pin when configured as a general
*                      purpose input pin                       
* FSXP[3]        - rw, Transmit frame-synchronization polarity bit
* FSRP[2]        - rw, Receive frame-synchronization polarity bit
* CLKXP[1]       - rw, Transmit clock polarity bit
* CLKRP[0]       - rw, Receive clock polarity bit 
*                                                                                   
\******************************************************************************/  
#define MCBSP_PCR_OFFSET            9
#define MCBSP_PCR0_ADDR             0x018C0024u
#define MCBSP_PCR1_ADDR             0x01900024u
#define MCBSP_PCR2_ADDR             0x01A40024u
#define MCBSP_PCR_DEFAULT           0x00000000u 

#define MCBSP_PCR_XIOEN_MASK        0x00002000u
#define MCBSP_PCR_XIOEN_SHIFT       0x0000000Du
#define MCBSP_PCR_XIOEN_DEFAULT     0x00000000u
#define MCBSP_PCR_XIOEN_SP          0x00000000u /* DX,FSX,CLKX are configured
                                                   as serial port pins */
#define MCBSP_PCR_XIOEN_GPIO        0x00000001u /* DX is configured as output;
                                                   FSX,CLKX are configured as
                                                   GPIO pins */

#define MCBSP_PCR_RIOEN_MASK        0x00001000u
#define MCBSP_PCR_RIOEN_SHIFT       0x0000000Cu
#define MCBSP_PCR_RIOEN_DEFAULT     0x00000000u
#define MCBSP_PCR_RIOEN_SP          0x00000000u /* DR,FSR,CLKR,CLKS pins are
                                                   configured as serial port
                                                   pins */
#define MCBSP_PCR_RIOEN_GPIO        0x00000001u /* DR,CLKS are configured as
                                                   input pins; FSR,CLKR are
                                                   configured as GPIO pins */

#define MCBSP_PCR_FSXM_MASK         0x00000800u
#define MCBSP_PCR_FSXM_SHIFT        0x0000000Bu
#define MCBSP_PCR_FSXM_DEFAULT      0x00000000u
#define MCBSP_PCR_FSXM_EXTERNAL     0x00000000u /* FSX_int is derived from an
                                                   external source */
#define MCBSP_PCR_FSXM_INTERNAL     0x00000001u /* FSX_int is determined by FSGM
                                                   bit in SRGR */

#define MCBSP_PCR_FSRM_MASK         0x00000400u
#define MCBSP_PCR_FSRM_SHIFT        0x0000000Au
#define MCBSP_PCR_FSRM_DEFAULT      0x00000000u
#define MCBSP_PCR_FSRM_EXTERNAL     0x00000000u /* FSR_int is derived from an
                                                   external source */
#define MCBSP_PCR_FSRM_INTERNAL     0x00000001u /* FSR_int is generated internal
                                                   by sample-rate generator */

#define MCBSP_PCR_CLKXM_MASK        0x00000200u
#define MCBSP_PCR_CLKXM_SHIFT       0x00000009u
#define MCBSP_PCR_CLKXM_DEFAULT     0x00000000u
#define MCBSP_PCR_CLKXM_INPUT       0x00000000u /* CLKX is an input pin and is
                                                   driven by an external clock*/
#define MCBSP_PCR_CLKXM_OUTPUT      0x00000001u /* CLKX is an output pin and is
                                                   driven by the internal sample
                                                   rate generator */

#define MCBSP_PCR_CLKRM_MASK        0x00000100u
#define MCBSP_PCR_CLKRM_SHIFT       0x00000008u
#define MCBSP_PCR_CLKRM_DEFAULT     0x00000000u
#define MCBSP_PCR_CLKRM_INPUT       0x00000000u /* CLKR is an input pin and is
                                                   driven by an external clock*/
#define MCBSP_PCR_CLKRM_OUTPUT      0x00000001u /* CLKR is an output pin and is
                                                   driven by the internal sample
                                                   rate generator */

#define MCBSP_PCR_CLKSSTAT_MASK     0x00000040u
#define MCBSP_PCR_CLKSSTAT_SHIFT    0x00000006u
#define MCBSP_PCR_CLKSSTAT_DEFAULT  0x00000000u
#define MCBSP_PCR_CLKSSTAT_0        0x00000000u /* CLKS pin is a logic low */
#define MCBSP_PCR_CLKSSTAT_1        0x00000001u /* CLKS pin is a logic high */

#define MCBSP_PCR_DXSTAT_MASK       0x00000020u
#define MCBSP_PCR_DXSTAT_SHIFT      0x00000005u
#define MCBSP_PCR_DXSTAT_DEFAULT    0x00000000u
#define MCBSP_PCR_DXSTAT_0          0x00000000u /* DX pin is a logic low */
#define MCBSP_PCR_DXSTAT_1          0x00000001u /* DX pin is a logic high */

#define MCBSP_PCR_DRSTAT_MASK       0x00000010u
#define MCBSP_PCR_DRSTAT_SHIFT      0x00000004u
#define MCBSP_PCR_DRSTAT_DEFAULT    0x00000000u
#define MCBSP_PCR_DRSTAT_0          0x00000000u /* DR pin is a logic low */
#define MCBSP_PCR_DRSTAT_1          0x00000001u /* DR pin is a logic high */

#define MCBSP_PCR_FSXP_MASK         0x00000008u
#define MCBSP_PCR_FSXP_SHIFT        0x00000003u
#define MCBSP_PCR_FSXP_DEFAULT      0x00000000u
#define MCBSP_PCR_FSXP_ACTIVEHIGH   0x00000000u /* Transmit frame sync pulse
                                                   is active high */
#define MCBSP_PCR_FSXP_ACTIVELOW    0x00000001u /* Transmit frame sync pulse
                                                   is active low */

#define MCBSP_PCR_FSRP_MASK         0x00000004u
#define MCBSP_PCR_FSRP_SHIFT        0x00000002u
#define MCBSP_PCR_FSRP_DEFAULT      0x00000000u
#define MCBSP_PCR_FSRP_ACTIVEHIGH   0x00000000u /* Receive frame sync pulse    
                                                   is active high */            
#define MCBSP_PCR_FSRP_ACTIVELOW    0x00000001u /* Receive frame sync pulse    
                                                   is active low */             
#define MCBSP_PCR_CLKXP_MASK        0x00000002u
#define MCBSP_PCR_CLKXP_SHIFT       0x00000001u
#define MCBSP_PCR_CLKXP_DEFAULT     0x00000000u
#define MCBSP_PCR_CLKXP_RISING      0x00000000u /* Transmit data sampled on
                                                   rising edge of CLKX */
#define MCBSP_PCR_CLKXP_FALLING     0x00000001u /* Transmit data sampled on
                                                   falling edge of CLKX */

#define MCBSP_PCR_CLKRP_MASK        0x00000001u
#define MCBSP_PCR_CLKRP_SHIFT       0x00000000u
#define MCBSP_PCR_CLKRP_DEFAULT     0x00000000u
#define MCBSP_PCR_CLKRP_FALLING     0x00000000u /* Receive data sampled on     
                                                   falling edge of CLKR */       
#define MCBSP_PCR_CLKRP_RISING      0x00000001u /* Receive data sampled on     
                                                   rising edge of CLKR */      
/*----------------------------------------------------------------------------*/

/******************************************************************************\
* McBSP Raw Registers Access Macro Definitions
\******************************************************************************/
#define MCBSP_RSET(REG,x)           (*(volatile Uint32*)(MCBSP_##REG##_ADDR))=((Uint32)(x))
#define MCBSP_RGET(REG)             (Uint32)(*(volatile Uint32*)(MCBSP_##REG##_ADDR))

#define MCBSP_FSET(N,REG,FIELD,x)   MCBSP_RSET(##REG##N, (MCBSP_RGET(##REG##N) & ~MCBSP_##REG##_##FIELD##_MASK) \
                                    | (((Uint32)(x) << MCBSP_##REG##_##FIELD##_SHIFT) & MCBSP_##REG##_##FIELD##_MASK))

#define MCBSP_FGET(N,REG,FIELD)     (Uint32)((((Uint32)(*(volatile Uint32*)(MCBSP_##REG##N##_ADDR))) \
                                    & MCBSP_##REG##_##FIELD##_MASK) >> MCBSP_##REG##_##FIELD##_SHIFT) 
/*----------------------------------------------------------------------------*/  

/******************************************************************************\
* Handle Based McBSP Register Macro Definitions
\******************************************************************************/
#define MCBSP_ADDRH(h,REG)          (Uint32)(&(h->baseAddr[MCBSP_##REG##_OFFSET])) 

#define MCBSP_RSETH(h,REG,x)        (*(volatile Uint32*)(MCBSP_ADDRH(h,##REG)))=((Uint32)(x))
#define MCBSP_RGETH(h,REG)          (*(volatile Uint32*)(MCBSP_ADDRH(h,##REG)))

#define MCBSP_FSETH(h,REG,FIELD,x)  MCBSP_RSETH(h,##REG, (MCBSP_RGETH(h,##REG) & ~MCBSP_##REG##_##FIELD##_MASK) \
                                    | (((Uint32)(x) << MCBSP_##REG##_##FIELD##_SHIFT) & MCBSP_##REG##_##FIELD##_MASK))

#define MCBSP_FGETH(h,REG,FIELD)    (Uint32)((((Uint32)(*(volatile Uint32*)(MCBSP_ADDRH(h,##REG)))) \
                                    & MCBSP_##REG##_##FIELD##_MASK) >> MCBSP_##REG##_##FIELD##_SHIFT) 
/*----------------------------------------------------------------------------*/

/******************************************************************************\
* McBSP Global Typedef Declarations
\******************************************************************************/
/* McBSP Port Handle Object */
typedef struct {
    Uint32          allocated;
    Uint32          xmtEventId;
    Uint32          rcvEventId;
    volatile Uint32 *baseAddr;
    Uint32          drrAddr;
    Uint32          dxrAddr;
} MCBSP_Handle;

/* McBSP Port Configuration Structure */
typedef struct {
    Uint32  spcr;
    Uint32  rcr;
    Uint32  xcr;
    Uint32  srgr;
    Uint32  mcr;
    Uint32  rcere0;
    Uint32  rcere1;
    Uint32  rcere2;
    Uint32  rcere3;
    Uint32  xcere0;
    Uint32  xcere1;
    Uint32  xcere2;
    Uint32  xcere3;
    Uint32  pcr;
} MCBSP_Config;
/*----------------------------------------------------------------------------*/

/******************************************************************************\
* McBSP global macro declarations
\******************************************************************************/                                  
/* McBSP Port Identifiers for Operation of the McBSP Port */
#define MCBSP_PORT0                 0
#define MCBSP_PORT1                 1
#define MCBSP_PORT2                 2

/* McBSP Device Identifiers for Operation of the McBSP Port */
#define MCBSP_DEV0                  MCBSP_PORT0
#define MCBSP_DEV1                  MCBSP_PORT1
#define MCBSP_DEV2                  MCBSP_PORT2

/* Constants for MCBSP_start */
#define MCBSP_RCV_START             0x00000001u
#define MCBSP_XMIT_START            0x00000002u
#define MCBSP_SRGR_START            0x00000004u
#define MCBSP_SRGR_FRAMESYNC        0x00000008u
#define MCBSP_SRGR_DEFAULT_DELAY    0xFFFFFFFFu

/* McBSP Port Pins are Configed as GPIO */
#define MCBSP_PIN_INPUT_MASK        (Uint32)(  MCBSP_PCR_CLKXP_MASK    \
                                             | MCBSP_PCR_FSXP_MASK     \
                                             | MCBSP_PCR_DXSTAT_MASK   \
                                             | MCBSP_PCR_CLKRP_MASK    \
                                             | MCBSP_PCR_FSRP_MASK     \
                                             | MCBSP_PCR_DRSTAT_MASK   \
                                             | MCBSP_PCR_CLKSSTAT_MASK )

#define MCBSP_PIN_OUTPUT_MASK       (Uint32)(  MCBSP_PCR_CLKXP_MASK    \
                                             | MCBSP_PCR_FSXP_MASK     \
                                             | MCBSP_PCR_DXSTAT_MASK   \
                                             | MCBSP_PCR_CLKRP_MASK    \
                                             | MCBSP_PCR_FSRP_MASK     )

/* Invalid Pointer to  McBSP Handle */
#define MCBSP_HINV                  ((void*)(-1))

#define MCBSP_DEVICE_ENTRY(portNum) {FALSE, \
                                    (Uint32)IRQ_EVT_XINT##portNum##, \
                                    (Uint32)IRQ_EVT_