bbu_dd_mcbspcsl.h

DSP芯片自检测程序

#define MCBSP_MCR_RMCME_MASK        0x00000200u
#define MCBSP_MCR_RMCME_SHIFT       0x00000009u
#define MCBSP_MCR_RMCME_DEFAULT     0x00000000u
#define MCBSP_MCR_RMCME_NORMAL      0x00000000u /* Normal 32 channel selection
                                                   is enabled */
#define MCBSP_MCR_RMCME_ENHANCED    0x00000001u /* Enhanced 128 channel     
                                                   selection is enabled */
                                                    
#define MCBSP_MCR_RPBBLK_MASK       0x00000180u
#define MCBSP_MCR_RPBBLK_SHIFT      0x00000007u
#define MCBSP_MCR_RPBBLK_DEFAULT    0x00000000u
#define MCBSP_MCR_RPBBLK_SF1        0x00000000u /* Channel 16 to channel 31 */  
#define MCBSP_MCR_RPBBLK_SF3        0x00000001u /* Channel 48 to channel 63 */  
#define MCBSP_MCR_RPBBLK_SF5        0x00000002u /* Channel 80 to channel 95 */  
#define MCBSP_MCR_RPBBLK_SF7        0x00000003u /* Channel 112 to channel 127 */

#define MCBSP_MCR_RPABLK_MASK       0x00000060u
#define MCBSP_MCR_RPABLK_SHIFT      0x00000005u
#define MCBSP_MCR_RPABLK_DEFAULT    0x00000000u
#define MCBSP_MCR_RPABLK_SF0        0x00000000u /* Channel 0 to channel 15 */   
#define MCBSP_MCR_RPABLK_SF2        0x00000001u /* Channel 32 to channel 47 */  
#define MCBSP_MCR_RPABLK_SF4        0x00000002u /* Channel 64 to channel 79 */  
#define MCBSP_MCR_RPABLK_SF6        0x00000003u /* Channel 96 to channel 111 */ 

#define MCBSP_MCR_RCBLK_MASK        0x0000001Cu
#define MCBSP_MCR_RCBLK_SHIFT       0x00000002u
#define MCBSP_MCR_RCBLK_DEFAULT     0x00000000u
#define MCBSP_MCR_RCBLK_SF0         0x00000000u /* Channel 0 to channel 15 */   
#define MCBSP_MCR_RCBLK_SF1         0x00000001u /* Channel 16 to channel 31 */  
#define MCBSP_MCR_RCBLK_SF2         0x00000002u /* Channel 32 to channel 47 */  
#define MCBSP_MCR_RCBLK_SF3         0x00000003u /* Channel 48 to channel 63 */  
#define MCBSP_MCR_RCBLK_SF4         0x00000004u /* Channel 64 to channel 79 */  
#define MCBSP_MCR_RCBLK_SF5         0x00000005u /* Channel 80 to channel 95 */  
#define MCBSP_MCR_RCBLK_SF6         0x00000006u /* Channel 96 to channel 111 */ 
#define MCBSP_MCR_RCBLK_SF7         0x00000007u /* Channel 112 to channel 127 */

#define MCBSP_MCR_RMCM_MASK         0x00000001u
#define MCBSP_MCR_RMCM_SHIFT        0x00000000u
#define MCBSP_MCR_RMCM_DEFAULT      0x00000000u
#define MCBSP_MCR_RMCM_CHENABLE     0x00000000u /* All 128 channel is enabled */
#define MCBSP_MCR_RMCM_ELDISABLE    0x00000001u /* All channels are disabled
                                                   by default */

/******************************************************************************\      
*       McBSP Ports Enhanced Receive Channel Enable Registers0 Definitions                      
* 
* RCERE00 - serial port 0 enhanced receive channel enable register 0
* RCERE01 - serial port 1 enhanced receive channel enable register 0
* RCERE02 - serial port 2 enhanced receive channel enable register 0
*                                                                                     
* RCE - rw 
* RCEx = "1", enable reception of a channel of 31--0 elements
* RCEx = "0", Disable reception of a channel of 31--0 elements
*                           
\******************************************************************************/  
#define MCBSP_RCERE0_OFFSET         7
#define MCBSP_RCERE00_ADDR          0x018C001Cu
#define MCBSP_RCERE01_ADDR          0x0190001Cu
#define MCBSP_RCERE02_ADDR          0x01A4001Cu
#define MCBSP_RCERE0_DEFAULT        0x00000000u

#define MCBSP_RCERE0_RCE_MASK       0xFFFFFFFFu
#define MCBSP_RCERE0_RCE_SHIFT      0x00000000u
#define MCBSP_RCERE0_RCE_DEFAULT    0x00000000u

/******************************************************************************\      
*       McBSP Ports Enhanced Receive Channel Enable Registers1 Definitions                      
* 
* RCERE10 - serial port 0 enhanced receive channel enable register 1
* RCERE11 - serial port 1 enhanced receive channel enable register 1
* RCERE12 - serial port 2 enhanced receive channel enable register 1
*                                                                                     
* RCE - rw 
* RCEx = "1", enable reception of a channel of 63--32 elements
* RCEx = "0", Disable reception of a channel of 63--32 elements
*                           
\******************************************************************************/  
#define MCBSP_RCERE1_OFFSET         10
#define MCBSP_RCERE10_ADDR          0x018C0028u
#define MCBSP_RCERE11_ADDR          0x01900028u
#define MCBSP_RCERE12_ADDR          0x01A40028u
#define MCBSP_RCERE1_DEFAULT        0x00000000u

#define MCBSP_RCERE1_RCE_MASK       0xFFFFFFFFu
#define MCBSP_RCERE1_RCE_SHIFT      0x00000000u
#define MCBSP_RCERE1_RCE_DEFAULT    0x00000000u
 
/******************************************************************************\      
*       McBSP Ports Enhanced Receive Channel Enable Registers2 Definitions                      
* 
* RCERE20 - serial port 0 enhanced receive channel enable register 2
* RCERE21 - serial port 1 enhanced receive channel enable register 2
* RCERE22 - serial port 2 enhanced receive channel enable register 2
*                                                                                     
* RCE - rw 
* RCEx = "1", enable reception of a channel of 95--64 elements
* RCEx = "0", Disable reception of a channel of 95--64 elements
*                           
\******************************************************************************/  
#define MCBSP_RCERE2_OFFSET         0xC
#define MCBSP_RCERE20_ADDR          0x018C0030u
#define MCBSP_RCERE21_ADDR          0x01900030u
#define MCBSP_RCERE22_ADDR          0x01A40030u
#define MCBSP_RCERE2_DEFAULT        0x00000000u

#define MCBSP_RCERE2_RCE_MASK       0xFFFFFFFFu
#define MCBSP_RCERE2_RCE_SHIFT      0x00000000u
#define MCBSP_RCERE2_RCE_DEFAULT    0x00000000u

/******************************************************************************\      
*       McBSP Ports Enhanced Receive Channel Enable Registers3 Definitions                      
* 
* RCERE30 - serial port 0 enhanced receive channel enable register 3
* RCERE31 - serial port 1 enhanced receive channel enable register 3
* RCERE32 - serial port 2 enhanced receive channel enable register 3
*                                                                                     
* RCE - rw 
* RCEx = "1", enable reception of a channel of 127--96 elements
* RCEx = "0", Disable reception of a channel of 127--96 elements
*                           
\******************************************************************************/   
#define MCBSP_RCERE3_OFFSET         0xE
#define MCBSP_RCERE30_ADDR          0x018C0038u
#define MCBSP_RCERE31_ADDR          0x01900038u
#define MCBSP_RCERE32_ADDR          0x01A40038u
#define MCBSP_RCERE3_DEFAULT        0x00000000u
#define MCBSP_RCERE3_RCE_MASK       0xFFFFFFFFu
#define MCBSP_RCERE3_RCE_SHIFT      0x00000000u
#define MCBSP_RCERE3_RCE_DEFAULT    0x00000000u

/******************************************************************************\      
*       McBSP Ports Enhanced Transmit Channel Enable Registers0 Definitions                      
* 
* XCERE00 - serial port 0 enhanced transmit channel enable register 0
* XCERE01 - serial port 1 enhanced transmit channel enable register 0
* XCERE02 - serial port 2 enhanced transmit channel enable register 0
*                                                                                     
* XCE - rw 
* XCEx = "1", enable transmission of a channel of 31--0 elements
* XCEx = "0", Disable transmission of a channel of 31--0 elements
*                           
\******************************************************************************/   
#define MCBSP_XCERE0_OFFSET         8
#define MCBSP_XCERE00_ADDR          0x018C0020u
#define MCBSP_XCERE01_ADDR          0x01900020u
#define MCBSP_XCERE02_ADDR          0x01A40020u
#define MCBSP_XCERE0_DEFAULT        0x00000000u

#define MCBSP_XCERE0_XCE_MASK       0xFFFFFFFFu
#define MCBSP_XCERE0_XCE_SHIFT      0x00000000u
#define MCBSP_XCERE0_XCE_DEFAULT    0x00000000u

/******************************************************************************\ 
*       McBSP Ports Enhanced Transmit Channel Enable Registers1 Definitions      
*                                                                                
* XCERE10 - serial port 0 enhanced transmit channel enable register 1
* XCERE11 - serial port 1 enhanced transmit channel enable register 1
* XCERE12 - serial port 2 enhanced transmit channel enable register 1
*                                                                                
* XCE - rw                                                                       
* XCEx = "1", enable transmission of a channel of 63--32 elements                 
* XCEx = "0", Disable transmission of a channel of 63--32 elements                
*                                                                                
\******************************************************************************/ 
#define MCBSP_XCERE1_OFFSET         0xB
#define MCBSP_XCERE10_ADDR          0x018C002Cu
#define MCBSP_XCERE11_ADDR          0x0190002Cu
#define MCBSP_XCERE12_ADDR          0x01A4002Cu
#define MCBSP_XCERE1_DEFAULT        0x00000000u

#define MCBSP_XCERE1_XCE_MASK       0xFFFFFFFFu
#define MCBSP_XCERE1_XCE_SHIFT      0x00000000u
#define MCBSP_XCERE1_XCE_DEFAULT    0x00000000u

/******************************************************************************\ 
*       McBSP Ports Enhanced Transmit Channel Enable Registers2 Definitions      
*                                                                                
* XCERE20 - serial port 0 enhanced transmit channel enable register 2
* XCERE21 - serial port 1 enhanced transmit channel enable register 2
* XCERE22 - serial port 2 enhanced transmit channel enable register 2
*                                                                                
* XCE - rw                                                                       
* XCEx = "1", enable transmission of a channel of 95--64 elements                 
* XCEx = "0", Disable transmission of a channel of 95--64 elements                
*                                                                                
\******************************************************************************/ 
#define MCBSP_XCERE2_OFFSET         0xD
#define MCBSP_XCERE20_ADDR          0x018C0034u
#define MCBSP_XCERE21_ADDR          0x01900034u
#define MCBSP_XCERE22_ADDR          0x01A40034u
#define MCBSP_XCERE2_DEFAULT        0x00000000u

#define MCBSP_XCERE2_XCE_MASK       0xFFFFFFFFu
#define MCBSP_XCERE2_XCE_SHIFT      0x00000000u
#define MCBSP_XCERE2_XCE_DEFAULT    0x00000000u

/******************************************************************************\ 
*       McBSP Ports Enhanced Transmit Channel Enable Registers3 Definitions      
*                                                                                
* XCERE30 - serial port 0 enhanced transmit channel enable register 3
* XCERE31 - serial port 1 enhanced transmit channel enable register 3
* XCERE32 - serial port 2 enhanced transmit channel enable register 3
*                                                                                
* XCE - rw                                                                       
* XCEx = "1", enable transmission of a channel of 127--96 elements                 
* XCEx = "0", Disable transmission of a channel of 127--96 elements                
*                                                                                
\******************************************************************************/ 
#define MCBSP_XCERE3_OFFSET         0xF
#define MCBSP_XCERE30_ADDR          0x018C003Cu
#define MCBSP_XCERE31_ADDR          0x0190003Cu
#define MCBSP_XCERE32_ADDR          0x01A4003Cu
#define MCBSP_XCERE3_DEFAULT        0x00000000u

#define MCBSP_XCERE3_XCE_MASK       0xFFFFFFFFu
#define MCBSP_XCERE3_XCE_SHIFT      0x00000000u
#define MCBSP_XCERE3_XCE_DEFAULT    0x00000000u

/******************************************************************************\    
*              McBSP Ports Pin Control Registers Definitions                    
*                                                                                   
* PCR0  - serial port 0 pin control register
* PCR1  - serial port 1 pin control register
* PCR2  - serial port 2 pin control register
*                                                                                   
* XIOEN[13]      - rw, Transmit GPIO mode when transmitter is disabled (XRST=0)                                           
* RIOEN[12]      - rw, Receive GPIO mode when receiver is disabled (RRST = 0)