📄 bbu_dd_mcbspcsl.h
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* XDATDLY[17:16] - rw, Transmit data delay bit
* XFRLEN1[14:8] - rw, Specifies the transmit frame length (number of words)
* in phase 1
* XWDLEN1[7:5] - rw, Specifies the transmit word length (number of bits)
* in phase 1.
* XWDREVRS[4] - rw, Transmit 32-bit bit reversal enable bit
*
\******************************************************************************/
#define MCBSP_XCR_OFFSET 4
#define MCBSP_XCR0_ADDR 0x01840010u
#define MCBSP_XCR1_ADDR 0x01900010u
#define MCBSP_XCR2_ADDR 0x01A40010u
#define MCBSP_XCR_DEFAULT 0x00000000u
#define MCBSP_XCR_XPHASE_MASK 0x80000000u
#define MCBSP_XCR_XPHASE_SHIFT 0x0000001Fu
#define MCBSP_XCR_XPHASE_DEFAULT 0x00000000u
#define MCBSP_XCR_XPHASE_SINGLE 0x00000000u /* Single-phase frame */
#define MCBSP_XCR_XPHASE_DUAL 0x00000001u /* Dual-phase frame */
#define MCBSP_XCR_XFRLEN2_MASK 0x7F000000u
#define MCBSP_XCR_XFRLEN2_SHIFT 0x00000018u
#define MCBSP_XCR_XFRLEN2_DEFAULT 0x00000000u
#define MCBSP_XCR_XWDLEN2_MASK 0x00E00000u
#define MCBSP_XCR_XWDLEN2_SHIFT 0x00000015u
#define MCBSP_XCR_XWDLEN2_DEFAULT 0x00000000u
#define MCBSP_XCR_XWDLEN2_8BIT 0x00000000u /* word length is 8 bits */
#define MCBSP_XCR_XWDLEN2_12BIT 0x00000001u /* word length is 12 bits */
#define MCBSP_XCR_XWDLEN2_16BIT 0x00000002u /* word length is 16 bits */
#define MCBSP_XCR_XWDLEN2_20BIT 0x00000003u /* word length is 20 bits */
#define MCBSP_XCR_XWDLEN2_24BIT 0x00000004u /* word length is 24 bits */
#define MCBSP_XCR_XWDLEN2_32BIT 0x00000005u /* word length is 32 bits */
#define MCBSP_XCR_XCOMPAND_MASK 0x00180000u
#define MCBSP_XCR_XCOMPAND_SHIFT 0x00000013u
#define MCBSP_XCR_XCOMPAND_DEFAULT 0x00000000u
#define MCBSP_XCR_XCOMPAND_MSB 0x00000000u /* No companding, data transfer
starts with MSB first */
#define MCBSP_XCR_XCOMPAND_8BITLSB 0x00000001u /* No companding, 8bit data
transfer starts with LSB */
#define MCBSP_XCR_XCOMPAND_ULAW 0x00000002u /* Compand using μ-law */
#define MCBSP_XCR_XCOMPAND_ALAW 0x00000003u /* Compand using A-law */
#define MCBSP_XCR_XFIG_MASK 0x00040000u
#define MCBSP_XCR_XFIG_SHIFT 0x00000012u
#define MCBSP_XCR_XFIG_DEFAULT 0x00000000u
#define MCBSP_XCR_XFIG_NO 0x00000000u /* Transmit FSX after the first
FSX pulse restart transfer */
#define MCBSP_XCR_XFIG_YES 0x00000001u /* Transmit FSX after the first
FSX pulse are ignored */
#define MCBSP_XCR_XDATDLY_MASK 0x00030000u
#define MCBSP_XCR_XDATDLY_SHIFT 0x00000010u
#define MCBSP_XCR_XDATDLY_DEFAULT 0x00000000u
#define MCBSP_XCR_XDATDLY_0BIT 0x00000000u /* 0 bit data delay */
#define MCBSP_XCR_XDATDLY_1BIT 0x00000001u /* 1 bit data delay */
#define MCBSP_XCR_XDATDLY_2BIT 0x00000002u /* 2 bit data delay */
#define MCBSP_XCR_XFRLEN1_MASK 0x00007F00u
#define MCBSP_XCR_XFRLEN1_SHIFT 0x00000008u
#define MCBSP_XCR_XFRLEN1_DEFAULT 0x00000000u
#define MCBSP_XCR_XWDLEN1_MASK 0x000000E0u
#define MCBSP_XCR_XWDLEN1_SHIFT 0x00000005u
#define MCBSP_XCR_XWDLEN1_DEFAULT 0x00000000u
#define MCBSP_XCR_XWDLEN1_8BIT 0x00000000u /* word length is 8 bits */
#define MCBSP_XCR_XWDLEN1_12BIT 0x00000001u /* word length is 12 bits */
#define MCBSP_XCR_XWDLEN1_16BIT 0x00000002u /* word length is 16 bits */
#define MCBSP_XCR_XWDLEN1_20BIT 0x00000003u /* word length is 20 bits */
#define MCBSP_XCR_XWDLEN1_24BIT 0x00000004u /* word length is 24 bits */
#define MCBSP_XCR_XWDLEN1_32BIT 0x00000005u /* word length is 32 bits */
#define MCBSP_XCR_XWDREVRS_MASK 0x00000010u
#define MCBSP_XCR_XWDREVRS_SHIFT 0x00000004u
#define MCBSP_XCR_XWDREVRS_DEFAULT 0x00000000u
#define MCBSP_XCR_XWDREVRS_DISABLE 0x00000000u /* 32bit reversal is disabled */
#define MCBSP_XCR_XWDREVRS_ENABLE 0x00000001u /* 32bit reversal is enabled */
/******************************************************************************\
* McBSP Ports Sample Rate Generator Registers Definitions
*
* SRGR0 - serial port 0 sample rate generator register
* SRGR1 - serial port 1 sample rate generator register
* SRGR2 - serial port 2 sample rate generator register
*
* GSYNC[31] - rw, Sample rate generator clock synchronization bit, is only
* used when the external clock CLKS drives the sample rate
* generator clock (CLKSM = 0)
* CLKSP[30] - rw, CLKS polarity clock edge select bit, is only used when
* the external clock CLKS drives the sample rate generator
* clock (CLKSM = 0)
* CLKSM[29] - rw, sample rate generator clock mode bit
* FSGM[28] - rw, Sample rate generator transmit frame synchronization mode
* bit, is only used when FSXM = 1 in PCR
* FPER[27:16] - rw, Specifies frame period value is FPER plus 1 CLKG periods
* FWID[15:8] - rw, Specifies FSG width value is FWID plus 1 CLKG periods
* CLKGDV[7:0] - rw, CLKG divider value, CLKG is 1/(CLKGDV + 1) of the sample
* rate generator input clock
*
\******************************************************************************/
#define MCBSP_SRGR_OFFSET 5
#define MCBSP_SRGR0_ADDR 0x018C0014u
#define MCBSP_SRGR1_ADDR 0x01900014u
#define MCBSP_SRGR2_ADDR 0x01A40014u
#define MCBSP_SRGR_DEFAULT 0x20000001u
#define MCBSP_SRGR_GSYNC_MASK 0x80000000u
#define MCBSP_SRGR_GSYNC_SHIFT 0x0000001Fu
#define MCBSP_SRGR_GSYNC_DEFAULT 0x00000000u
#define MCBSP_SRGR_GSYNC_FREE 0x00000000u /* CLKG is free running */
#define MCBSP_SRGR_GSYNC_SYNC 0x00000001u /* CLKG is is resynchronized */
#define MCBSP_SRGR_CLKSP_MASK 0x40000000u
#define MCBSP_SRGR_CLKSP_SHIFT 0x0000001Eu
#define MCBSP_SRGR_CLKSP_DEFAULT 0x00000000u
#define MCBSP_SRGR_CLKSP_RISING 0x00000000u /* Rising edge of CLKS generates
CLKG and FSG */
#define MCBSP_SRGR_CLKSP_FALLING 0x00000001u /* Falling edge of CLKS generates
CLKG and FSG */
#define MCBSP_SRGR_CLKSM_MASK 0x20000000u
#define MCBSP_SRGR_CLKSM_SHIFT 0x0000001Du
#define MCBSP_SRGR_CLKSM_DEFAULT 0x00000001u
#define MCBSP_SRGR_CLKSM_CLKS 0x00000000u /* CLKG clock is derived from
the CLKS pin */
#define MCBSP_SRGR_CLKSM_INTERNAL 0x00000001u /* CLKG clock is derived from
CPU clock */
#define MCBSP_SRGR_FSGM_MASK 0x10000000u
#define MCBSP_SRGR_FSGM_SHIFT 0x0000001Cu
#define MCBSP_SRGR_FSGM_DEFAULT 0x00000000u
#define MCBSP_SRGR_FSGM_DXR2XSR 0x00000000u /* FSX is generated on every
DXR-to-XSR copy */
#define MCBSP_SRGR_FSGM_FSG 0x00000001u /* FSX is driven by the sample
rate generator FSG */
#define MCBSP_SRGR_FPER_MASK 0x0FFF0000u
#define MCBSP_SRGR_FPER_SHIFT 0x00000010u
#define MCBSP_SRGR_FPER_DEFAULT 0x00000000u
#define MCBSP_SRGR_FWID_MASK 0x0000FF00u
#define MCBSP_SRGR_FWID_SHIFT 0x00000008u
#define MCBSP_SRGR_FWID_DEFAULT 0x00000000u
#define MCBSP_SRGR_CLKGDV_MASK 0x000000FFu
#define MCBSP_SRGR_CLKGDV_SHIFT 0x00000000u
#define MCBSP_SRGR_CLKGDV_DEFAULT 0x00000001u
/******************************************************************************\
* McBSP Ports Multichannel Control Registers Definitions
*
* MCR0 - serial port 0 multichannel control register
* MCR1 - serial port 1 multichannel control register
* MCR2 - serial port 2 multichannel control register
*
* XMCME[25] - rw, Transmit 128 channel selection enable bit, works in
* conjunction with the RMCME bit
* XPBBLK[24:23] - rw, Transmit partition B subframe bit. Enables 16 contiguous
* channels in each subframe
* XPABLK[22:21] - rw, Transmit partition A subframe bit. Enables 16 contiguous
* channels in each subframe
* XCBLK[20:18] - r, Transmit current subframe bit
* XMCM[17:16] - rw, Transmit multichannel selection enable bit
* RMCME[9] - rw, Receive 128 channel selection enable bit works with
* the XMCME bit
* RPBBLK[8:7] - rw, Receive partition B subframe bit. Enables 16 contiguous
* channels in each subframe
* RPABLK[6:5] - rw, Receive partition A subframe bit. Enables 16 contiguous
* channels in each subframe
* RCBLK[4:2] - r, Receive current subframe bit
* RMCM[0] - rw, Receive multichannel selection enable bit
*
\******************************************************************************/
#define MCBSP_MCR_OFFSET 6
#define MCBSP_MCR0_ADDR 0x018C0018u
#define MCBSP_MCR1_ADDR 0x01900018u
#define MCBSP_MCR2_ADDR 0x01A40018u
#define MCBSP_MCR_DEFAULT 0x00000000u
#define MCBSP_MCR_XMCME_MASK 0x02000000u
#define MCBSP_MCR_XMCME_SHIFT 0x00000019u
#define MCBSP_MCR_XMCME_DEFAULT 0x00000000u
#define MCBSP_MCR_XMCME_NORMAL 0x00000000u /* Normal 32 channel selection
is enabled */
#define MCBSP_MCR_XMCME_ENHANCED 0x00000001u /* Enhanced 128 channel
selection is enabled */
#define MCBSP_MCR_XPBBLK_MASK 0x01800000u
#define MCBSP_MCR_XPBBLK_SHIFT 0x00000017u
#define MCBSP_MCR_XPBBLK_DEFAULT 0x00000000u
#define MCBSP_MCR_XPBBLK_SF1 0x00000000u /* Channel 16 to channel 31 */
#define MCBSP_MCR_XPBBLK_SF3 0x00000001u /* Channel 48 to channel 63 */
#define MCBSP_MCR_XPBBLK_SF5 0x00000002u /* Channel 80 to channel 95 */
#define MCBSP_MCR_XPBBLK_SF7 0x00000003u /* Channel 112 to channel 127 */
#define MCBSP_MCR_XPABLK_MASK 0x00600000u
#define MCBSP_MCR_XPABLK_SHIFT 0x00000015u
#define MCBSP_MCR_XPABLK_DEFAULT 0x00000000u
#define MCBSP_MCR_XPABLK_SF0 0x00000000u /* Channel 0 to channel 15 */
#define MCBSP_MCR_XPABLK_SF2 0x00000001u /* Channel 32 to channel 47 */
#define MCBSP_MCR_XPABLK_SF4 0x00000002u /* Channel 64 to channel 79 */
#define MCBSP_MCR_XPABLK_SF6 0x00000003u /* Channel 96 to channel 111 */
#define MCBSP_MCR_XCBLK_MASK 0x001C0000u
#define MCBSP_MCR_XCBLK_SHIFT 0x00000012u
#define MCBSP_MCR_XCBLK_DEFAULT 0x00000000u
#define MCBSP_MCR_XCBLK_SF0 0x00000000u /* Channel 0 to channel 15 */
#define MCBSP_MCR_XCBLK_SF1 0x00000001u /* Channel 16 to channel 31 */
#define MCBSP_MCR_XCBLK_SF2 0x00000002u /* Channel 32 to channel 47 */
#define MCBSP_MCR_XCBLK_SF3 0x00000003u /* Channel 48 to channel 63 */
#define MCBSP_MCR_XCBLK_SF4 0x00000004u /* Channel 64 to channel 79 */
#define MCBSP_MCR_XCBLK_SF5 0x00000005u /* Channel 80 to channel 95 */
#define MCBSP_MCR_XCBLK_SF6 0x00000006u /* Channel 96 to channel 111 */
#define MCBSP_MCR_XCBLK_SF7 0x00000007u /* Channel 112 to channel 127 */
#define MCBSP_MCR_XMCM_MASK 0x00030000u
#define MCBSP_MCR_XMCM_SHIFT 0x00000010u
#define MCBSP_MCR_XMCM_DEFAULT 0x00000000u
#define MCBSP_MCR_XMCM_ENNOMASK 0x00000000u /* All channels are enabled
without masking */
#define MCBSP_MCR_XMCM_DISXP 0x00000001u /* All channels are disabled */
#define MCBSP_MCR_XMCM_ENMASK 0x00000002u /* All channels are enabled
but masked */
#define MCBSP_MCR_XMCM_DISRP 0x00000003u /* Used for symmetric transmit
and receive operation */
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