📄 bbu_dd_mcbspcsl.h
字号:
end-of-word and end-of-frame
in A-bis mode */
#define MCBSP_SPCR_XINTM_EOS 0x00000001u /* XINT is generated by
end-of-block or end-of-frame
in multichannel operation */
#define MCBSP_SPCR_XINTM_FRM 0x00000002u /* XINT is generated by a new
frame synchronization */
#define MCBSP_SPCR_XINTM_XSYNCERR 0x00000003u /* XINT is generated by
XSYNCERR */
#define MCBSP_SPCR_XSYNCERR_MASK 0x00080000u
#define MCBSP_SPCR_XSYNCERR_SHIFT 0x00000013u
#define MCBSP_SPCR_XSYNCERR_DEFAULT 0x00000000u
#define MCBSP_SPCR_XSYNCERR_NO 0x00000000u /* No synchronization error
is detected */
#define MCBSP_SPCR_XSYNCERR_YES 0x00000001u /* Synchronization error
is detected */
#define MCBSP_SPCR_XEMPTY_MASK 0x00040000u
#define MCBSP_SPCR_XEMPTY_SHIFT 0x00000012u
#define MCBSP_SPCR_XEMPTY_DEFAULT 0x00000000u
#define MCBSP_SPCR_XEMPTY_YES 0x00000000u /* XSR is empty */
#define MCBSP_SPCR_XEMPTY_NO 0x00000001u /* XSR is not empty */
#define MCBSP_SPCR_XRDY_MASK 0x00020000u
#define MCBSP_SPCR_XRDY_SHIFT 0x00000011u
#define MCBSP_SPCR_XRDY_DEFAULT 0x00000000u
#define MCBSP_SPCR_XRDY_NO 0x00000000u /* Transmitter is not ready */
#define MCBSP_SPCR_XRDY_YES 0x00000001u /* Transmitter is ready for
new data in DXR */
#define MCBSP_SPCR_XRST_MASK 0x00010000u
#define MCBSP_SPCR_XRST_SHIFT 0x00000010u
#define MCBSP_SPCR_XRST_DEFAULT 0x00000000u
#define MCBSP_SPCR_XRST_YES 0x00000000u /* Serial port transmitter is
disabled and in reset state*/
#define MCBSP_SPCR_XRST_NO 0x00000001u /* Serial port transmitter is
enabled */
#define MCBSP_SPCR_DLB_MASK 0x00008000u
#define MCBSP_SPCR_DLB_SHIFT 0x0000000Fu
#define MCBSP_SPCR_DLB_DEFAULT 0x00000000u
#define MCBSP_SPCR_DLB_OFF 0x00000000u /* Digital loop back mode is
disabled */
#define MCBSP_SPCR_DLB_ON 0x00000001u /* Digital loop back mode is
enabled */
#define MCBSP_SPCR_RJUST_MASK 0x00006000u
#define MCBSP_SPCR_RJUST_SHIFT 0x0000000Du
#define MCBSP_SPCR_RJUST_DEFAULT 0x00000000u
#define MCBSP_SPCR_RJUST_RZF 0x00000000u /* Right justify and zero fill
MSBs in DRR */
#define MCBSP_SPCR_RJUST_RSE 0x00000001u /* Right justify and sign extend
MSBs in DRR */
#define MCBSP_SPCR_RJUST_LZF 0x00000002u /* Left justify and zero fill
LSBs in DRR */
#define MCBSP_SPCR_CLKSTP_MASK 0x00001800u
#define MCBSP_SPCR_CLKSTP_SHIFT 0x0000000Bu
#define MCBSP_SPCR_CLKSTP_DEFAULT 0x00000000u
#define MCBSP_SPCR_CLKSTP_DISABLE 0x00000000u /* Clock stop mode is disabled
Normal clocking for non-SPI
mode */
#define MCBSP_SPCR_CLKSTP_NODELAY 0x00000002u /* Clock starts without delay
in SPI mode */
#define MCBSP_SPCR_CLKSTP_DELAY 0x00000003u /* Clock starts with delay
in SPI mode */
#define MCBSP_SPCR_DXENA_MASK 0x00000080u
#define MCBSP_SPCR_DXENA_SHIFT 0x00000007u
#define MCBSP_SPCR_DXENA_DEFAULT 0x00000000u
#define MCBSP_SPCR_DXENA_OFF 0x00000000u /* DX enabler is off */
#define MCBSP_SPCR_DXENA_ON 0x00000001u /* DX enabler is on */
#define MCBSP_SPCR_RINTM_MASK 0x00000030u
#define MCBSP_SPCR_RINTM_SHIFT 0x00000004u
#define MCBSP_SPCR_RINTM_DEFAULT 0x00000000u
#define MCBSP_SPCR_RINTM_RRDY 0x00000000u /* RINT is driven by RRDY
end-of-word and end-of-frame
in A-bis mode */
#define MCBSP_SPCR_RINTM_EOS 0x00000001u /* RINT is generated by
end-of-block or end-of-frame
in multichannel operation */
#define MCBSP_SPCR_RINTM_FRM 0x00000002u /* RINT is generated by a new
frame synchronization */
#define MCBSP_SPCR_RINTM_RSYNCERR 0x00000003u /* RINT is generated by
RSYNCERR */
#define MCBSP_SPCR_RSYNCERR_MASK 0x00000008u
#define MCBSP_SPCR_RSYNCERR_SHIFT 0x00000003u
#define MCBSP_SPCR_RSYNCERR_DEFAULT 0x00000000u
#define MCBSP_SPCR_RSYNCERR_NO 0x00000000u /* No synchronization error
is detected */
#define MCBSP_SPCR_RSYNCERR_YES 0x00000001u /* Synchronization error
is detected */
#define MCBSP_SPCR_RFULL_MASK 0x00000004u
#define MCBSP_SPCR_RFULL_SHIFT 0x00000002u
#define MCBSP_SPCR_RFULL_DEFAULT 0x00000000u
#define MCBSP_SPCR_RFULL_NO 0x00000000u /* RBR is not in overrun
condition */
#define MCBSP_SPCR_RFULL_YES 0x00000001u /* DRR is not read, RBR is full
and RSR is also full with
new word */
#define MCBSP_SPCR_RRDY_MASK 0x00000002u
#define MCBSP_SPCR_RRDY_SHIFT 0x00000001u
#define MCBSP_SPCR_RRDY_DEFAULT 0x00000000u
#define MCBSP_SPCR_RRDY_NO 0x00000000u /* Receiver is not ready */
#define MCBSP_SPCR_RRDY_YES 0x00000001u /* Receiver is ready with data
to be read from DRR */
#define MCBSP_SPCR_RRST_MASK 0x00000001u
#define MCBSP_SPCR_RRST_SHIFT 0x00000000u
#define MCBSP_SPCR_RRST_DEFAULT 0x00000000u
#define MCBSP_SPCR_RRST_YES 0x00000000u /* The serial port receiver is
disabled and in reset state*/
#define MCBSP_SPCR_RRST_NO 0x00000001u /* The serial port receiver is
enabled */
/******************************************************************************\
* McBSP Ports Receive Control Registers Definitions
*
* RCR0 - serial port 0 receive control register
* RCR1 - serial port 1 receive control register
* RCR2 - serial port 2 receive control register
*
* RPHASE[31] - rw, Receive phases bit
* RFRLEN2[30:24] - rw, Specifies the receive frame length (number of words)
* in phase 2
* RWDLEN2[23:21] - rw, Specifies the receive word length (number of bits)
* in phase 2
* RCOMPAND[20:19]- rw, Receive companding mode bit
* RFIG[18] - rw, Receive frame ignore bit
* RDATDLY[17:16] - rw, Receive data delay bit
* RFRLEN1[14:8] - rw, Specifies the receive frame length (number of words)
* in phase 1
* RWDLEN1[7:5] - rw, Specifies the receive word length (number of bits)
* in phase 1.
* RWDREVRS[4] - rw, Receive 32-bit bit reversal enable bit
*
\******************************************************************************/
#define MCBSP_RCR_OFFSET 3
#define MCBSP_RCR0_ADDR 0x018C000Cu
#define MCBSP_RCR1_ADDR 0x0190000Cu
#define MCBSP_RCR2_ADDR 0x01A4000Cu
#define MCBSP_RCR_DEFAULT 0x00000000u
#define MCBSP_RCR_RPHASE_MASK 0x80000000u
#define MCBSP_RCR_RPHASE_SHIFT 0x0000001Fu
#define MCBSP_RCR_RPHASE_DEFAULT 0x00000000u
#define MCBSP_RCR_RPHASE_SINGLE 0x00000000u /* Single-phase frame */
#define MCBSP_RCR_RPHASE_DUAL 0x00000001u /* Dual-phase frame */
#define MCBSP_RCR_RFRLEN2_MASK 0x7F000000u
#define MCBSP_RCR_RFRLEN2_SHIFT 0x00000018u
#define MCBSP_RCR_RFRLEN2_DEFAULT 0x00000000u
#define MCBSP_RCR_RWDLEN2_MASK 0x00E00000u
#define MCBSP_RCR_RWDLEN2_SHIFT 0x00000015u
#define MCBSP_RCR_RWDLEN2_DEFAULT 0x00000000u
#define MCBSP_RCR_RWDLEN2_8BIT 0x00000000u /* word length is 8 bits */
#define MCBSP_RCR_RWDLEN2_12BIT 0x00000001u /* word length is 12 bits */
#define MCBSP_RCR_RWDLEN2_16BIT 0x00000002u /* word length is 16 bits */
#define MCBSP_RCR_RWDLEN2_20BIT 0x00000003u /* word length is 20 bits */
#define MCBSP_RCR_RWDLEN2_24BIT 0x00000004u /* word length is 24 bits */
#define MCBSP_RCR_RWDLEN2_32BIT 0x00000005u /* word length is 32 bits */
#define MCBSP_RCR_RCOMPAND_MASK 0x00180000u
#define MCBSP_RCR_RCOMPAND_SHIFT 0x00000013u
#define MCBSP_RCR_RCOMPAND_DEFAULT 0x00000000u
#define MCBSP_RCR_RCOMPAND_MSB 0x00000000u /* No companding, data transfer
starts with MSB first */
#define MCBSP_RCR_RCOMPAND_8BITLSB 0x00000001u /* No companding, 8bit data
transfer starts with LSB */
#define MCBSP_RCR_RCOMPAND_ULAW 0x00000002u /* Compand using μ-law */
#define MCBSP_RCR_RCOMPAND_ALAW 0x00000003u /* Compand using A-law */
#define MCBSP_RCR_RFIG_MASK 0x00040000u
#define MCBSP_RCR_RFIG_SHIFT 0x00000012u
#define MCBSP_RCR_RFIG_DEFAULT 0x00000000u
#define MCBSP_RCR_RFIG_NO 0x00000000u /* Receive FSR after the first
FSR pulse restart transfer */
#define MCBSP_RCR_RFIG_YES 0x00000001u /* Receive FSR after the first
FSR pulse are ignored */
#define MCBSP_RCR_RDATDLY_MASK 0x00030000u
#define MCBSP_RCR_RDATDLY_SHIFT 0x00000010u
#define MCBSP_RCR_RDATDLY_DEFAULT 0x00000000u
#define MCBSP_RCR_RDATDLY_0BIT 0x00000000u /* 0 bit data delay */
#define MCBSP_RCR_RDATDLY_1BIT 0x00000001u /* 1 bit data delay */
#define MCBSP_RCR_RDATDLY_2BIT 0x00000002u /* 2 bit data delay */
#define MCBSP_RCR_RFRLEN1_MASK 0x00007F00u
#define MCBSP_RCR_RFRLEN1_SHIFT 0x00000008u
#define MCBSP_RCR_RFRLEN1_DEFAULT 0x00000000u
#define MCBSP_RCR_RWDLEN1_MASK 0x000000E0u
#define MCBSP_RCR_RWDLEN1_SHIFT 0x00000005u
#define MCBSP_RCR_RWDLEN1_DEFAULT 0x00000000u
#define MCBSP_RCR_RWDLEN1_8BIT 0x00000000u /* word length is 8 bits */
#define MCBSP_RCR_RWDLEN1_12BIT 0x00000001u /* word length is 12 bits */
#define MCBSP_RCR_RWDLEN1_16BIT 0x00000002u /* word length is 16 bits */
#define MCBSP_RCR_RWDLEN1_20BIT 0x00000003u /* word length is 20 bits */
#define MCBSP_RCR_RWDLEN1_24BIT 0x00000004u /* word length is 24 bits */
#define MCBSP_RCR_RWDLEN1_32BIT 0x00000005u /* word length is 32 bits */
#define MCBSP_RCR_RWDREVRS_MASK 0x00000010u
#define MCBSP_RCR_RWDREVRS_SHIFT 0x00000004u
#define MCBSP_RCR_RWDREVRS_DEFAULT 0x00000000u
#define MCBSP_RCR_RWDREVRS_DISABLE 0x00000000u /* 32bit reversal is disabled */
#define MCBSP_RCR_RWDREVRS_ENABLE 0x00000001u /* 32bit reversal is enabled */
/******************************************************************************\
* McBSP Ports Receive Control Registers Definitions
*
* XCR0 - serial port 0 transmit control register
* XCR1 - serial port 1 transmit control register
* XCR2 - serial port 2 transmit control register
*
* XPHASE[31] - rw, Transmit phases bit
* XFRLEN2[30:24] - rw, Specifies the transmit frame length (number of words)
* in phase 2
* XWDLEN2[23:21] - rw, Specifies the transmit word length (number of bits)
* in phase 2
* XCOMPAND[20:19]- rw, Transmit companding mode bit
* XFIG[18] - rw, Transmit frame ignore bit
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