bbu_dd_hpicsl.h

DSP芯片自检测程序

/*******************************************************************************
* COPYRIGHT (C)             中国普天研究院									   *
********************************************************************************
* 源文件名: BBU_DD_HpiCsl.h                                                    *
* 功能描述：Registers Description for HPI in TMS320C6414 and TMS320C6416       *
* 编写者：louyj                                                                *
* 版本：1.0.0                                                                  *
* 编制日期：08/02/2004                                                         *
* 说明：                                                                       *
* 修改历史：                                                                   *
*                                                                              *
*******************************************************************************/

/*------------------------------------------------------------------------------
* Registers Descriptions for HPI in TMS320C6414 and TMS320C6416
*-------------------------------------------------------------------------------
*
* HPIC  - HPI control register
* HPIAW - HPI Address Write register
* HPIAR - HPI Address Read registrer
* TRCTL - TR Control register
*
\******************************************************************************/
#ifndef _BBU_DD_HPICSL_H_
#define _BBU_DD_HPICSL_H_

#include "BBU_DD_Stdinc.h"
#include "BBU_DD_IrqCsl.h"

/******************************************************************************\
* HPI Base Address Definitions 
\******************************************************************************/
#define HPI_BASE_ADDR               0x01880000u 
/*----------------------------------------------------------------------------*/

/******************************************************************************\
*                 HPI register Definitions
*
* HPIC  - HPI control register
*
* FETCH[4]       - r,  Host fetch request bit
* HRDY[3]        - r,  Ready signal to host bit
* HINT[2]        - rw, DSP-to-host interrupt bit
* DSPINT[1]      - rw, The host processor-to-DSP CPU/DMA interrupt bit
* HWOB[0]        - r,  Halfword ordering bit affects both data and address
*                      transfers. Only the host can modify this bit. For HPI32,
*                      HWOB is not used and the value of HWOB is irrelevant
*
\******************************************************************************/
#define HPI_HPIC_OFFSET             0
#define HPI_HPIC_ADDR               0x01880000u 
#define HPI_HPIC_DEFAULT            0x00000008u 

#define HPI_HPIC_FETCH_MASK         0x00000010u
#define HPI_HPIC_FETCH_SHIFT        0x00000004u
#define HPI_HPIC_FETCH_DEFAULT      0x00000000u
#define HPI_HPIC_FETCH_0            0x00000000u /* The value read by host or CPU
                                                   is always 0 */
#define HPI_HPIC_FETCH_1            0x00000001u /* The host writes  1 to the bit
                                                   to request a fetch into HPID
                                                   of the word at the address
                                                   pointed to by HPIA */
                                                                               
#define HPI_HPIC_HRDY_MASK          0x00000008u
#define HPI_HPIC_HRDY_SHIFT         0x00000003u
#define HPI_HPIC_HRDY_DEFAULT       0x00000001u
#define HPI_HPIC_HRDY_0             0x00000000u /* The internal bus is waiting
                                                   for an HPI data access request
                                                   to finish */
#define HPI_HPIC_HRDY_1             0x00000001u 

#define HPI_HPIC_HINT_MASK          0x00000004u
#define HPI_HPIC_HINT_SHIFT         0x00000002u
#define HPI_HPIC_HINT_DEFAULT       0x00000000u
#define HPI_HPIC_HINT_0             0x00000000u /* DSP HINT# output is logic 1 */
#define HPI_HPIC_HINT_1             0x00000001u /* DSP HINT# output is logic 0 */

#define HPI_HPIC_DSPINT_MASK        0x00000002u
#define HPI_HPIC_DSPINT_SHIFT       0x00000001u
#define HPI_HPIC_DSPINT_DEFAULT     0x00000000u
#define HPI_HPIC_DSPINT_0           0x00000000u
#define HPI_HPIC_DSPINT_1           0x00000001u

#define HPI_HPIC_HWOB_MASK          0x00000001u
#define HPI_HPIC_HWOB_SHIFT         0x00000000u
#define HPI_HPIC_HWOB_DEFAULT       0x00000000u
#define HPI_HPIC_HWOB_0             0x00000000u /* The first halfword is
                                                   most significant */
#define HPI_HPIC_HWOB_1             0x00000001u /* The first halfword is
                                                   least significant */

/******************************************************************************\
*                 HPI register Definitions
*
* HPIAW - HPI Address Write register
*
* HPIAW          - rw
*
\******************************************************************************/
#define HPI_HPIAW_OFFSET            1
#define HPI_HPIAW_ADDR              0x01880004u
#define HPI_HPIAW_DEFAULT           0x00000000u

#define HPI_HPIAW_HPIAW_MASK        0xFFFFFFFCu
#define HPI_HPIAW_HPIAW_SHIFT       0x00000000u
#define HPI_HPIAW_HPIAW_DEFAULT     0x00000000u

/******************************************************************************\
*                 HPI register Definitions
*
* HPIAR - HPI Address Read register
*
* HPIAR          - rw
*
\******************************************************************************/
#define HPI_HPIAR_OFFSET            2
#define HPI_HPIAR_ADDR              0x01880008u
#define HPI_HPIAR_DEFAULT           0x00000000u
#define HPI_HPIAR_HPIAR_MASK        0xFFFFFFFCu
#define HPI_HPIAR_HPIAR_SHIFT       0x00000000u
#define HPI_HPIAR_HPIAR_DEFAULT     0x00000000u

/******************************************************************************\
*                 HPI register Definitions
*
* TRCTL - HPI transfer request Control register
*
* TRSTALL[8]     - rw, Forces the HPI to stall all HPI requests to the EDMA.
*                      This bit allows the safe changing of the PALLOC and PRI
* PRI[5:4]       - rw, Controls the priority queue level that HPI requests are
*                      submitted to
* PALLOC[3:0]    - rw, Controls the total number of outstanding requests that
*                      can be submitted by the HPI to the EDMA 
*
\******************************************************************************/
#define HPI_TRCTL_OFFSET            32768
#define HPI_TRCTL_ADDR              0x018A0000u
#define HPI_TRCTL_DEFAULT           0x00000024u

#define HPI_TRCTL_TRSTALL_MASK      0x00000100u
#define HPI_TRCTL_TRSTALL_SHIFT     0x00000008u
#define HPI_TRCTL_TRSTALL_DEFAULT   0x00000000u
#define HPI_TRCTL_TRSTALL_ALLOW     0x00000000u
#define HPI_TRCTL_TRSTALL_HALT      0x00000001u

#define HPI_TRCTL_PRI_MASK          0x00000030u
#define HPI_TRCTL_PRI_SHIFT         0x00000004u
#define HPI_TRCTL_PRI_DEFAULT       0x00000002u
#define HPI_TRCTL_PRI_URGENT        0x00000000u
#define HPI_TRCTL_PRI_HIGH          0x00000001u
#define HPI_TRCTL_PRI_MEDIUM        0x00000002u
#define HPI_TRCTL_PRI_LOW           0x00000003u

#define HPI_TRCTL_PALLOC_MASK       0x0000000Fu
#define HPI_TRCTL_PALLOC_SHIFT      0x00000000u
#define HPI_TRCTL_PALLOC_DEFAULT    0x00000004u
/*----------------------------------------------------------------------------*/

/******************************************************************************\
* HPI Raw Registers Access Macro Definitions
\******************************************************************************/
#define HPI_RSET(REG,x)             (*(volatile Uint32*)(HPI_##REG##_ADDR))=((Uint32)(x))
#define HPI_RGET(REG)               (Uint32)(*(volatile Uint32*)(HPI_##REG##_ADDR))

#define HPI_FSET(REG,FIELD,x)       HPI_RSET(##REG, (HPI_RGET(##REG) & ~HPI_##REG##_##FIELD##_MASK) \
                                    | (((Uint32)(x) << HPI_##REG##_##FIELD##_SHIFT) & HPI_##REG##_##FIELD##_MASK))

#define HPI_FGET(REG,FIELD)         (Uint32)((((Uint32)(*(volatile Uint32*)(HPI_##REG##_ADDR))) \
                                    & HPI_##REG##_##FIELD##_MASK) >> HPI_##REG##_##FIELD##_SHIFT) 
/*----------------------------------------------------------------------------*/

/******************************************************************************\
* HPI inline function declarations
\******************************************************************************/
IDECL Uint32 HPI_getEventId(void);
IDECL Uint32 HPI_getHwob(void);
IDECL Uint32 HPI_getDspint(void);
IDECL Uint32 HPI_getHint(void);
IDECL Uint32 HPI_getHrdy(void);
IDECL Uint32 HPI_getFetch(void);
IDECL void   HPI_setDspint(Uint32 val);
IDECL void   HPI_setHint(Uint32 val);
IDECL void   HPI_setWriteAddr(Uint32 address);
IDECL Uint32 HPI_getWriteAddr(void);
IDECL void   HPI_setReadAddr(Uint32 address);
IDECL Uint32 HPI_getReadAddr(void);

/******************************************************************************\
* HPI inline function definitions
\******************************************************************************/
/* Obtain the IRQ event associated with the HPI device */
IDECL Uint32 HPI_getEventId(void)
{
  return (Uint32)IRQ_EVT_DSPINT;
}
/*----------------------------------------------------------------------------*/

/* Returns the value of the HWOB bit of the HPIC register */
IDECL Uint32 HPI_getHwob(void)
{
  return HPI_FGET(HPIC,HWOB);
}
/*----------------------------------------------------------------------------*/

/* This function reads the DSPINT bit from the HPIC register */
IDECL Uint32 HPI_getDspint(void)
{
  return HPI_FGET(HPIC,DSPINT);
}
/*----------------------------------------------------------------------------*/

/* This function returns the value of the HINT bit of the HPIC register */
IDECL Uint32 HPI_getHint(void)
{
  return HPI_FGET(HPIC,HINT);
}
/*----------------------------------------------------------------------------*/

/* This function returns the value of the HRDY bit of the HPIC register */
IDECL Uint32 HPI_getHrdy(void)
{
  return HPI_FGET(HPIC,HRDY);
}
/*----------------------------------------------------------------------------*/

/* This function reads the FETCH from the HPIC register and returns value 0 */
IDECL Uint32 HPI_getFetch(void)
{
  return HPI_FGET(HPIC,FETCH);
}
/*----------------------------------------------------------------------------*/

/* This function writes the value to the DSPINT filed of the HPIC register */
IDECL void HPI_setDspint(Uint32 val)
{
  HPI_FSET(HPIC,DSPINT,val);
}
/*----------------------------------------------------------------------------*/

/* This function writes the value to the HINT filed of the HPIC register */
IDECL void HPI_setHint(Uint32 val)
{
  HPI_FSET(HPIC,HINT,val);
}
/*----------------------------------------------------------------------------*/

/* This function sets the write memory address in the HPIAW register */
IDECL void HPI_setWriteAddr(Uint32 address)
{
  HPI_FSET(HPIAW,HPIAW,address);
}
/*----------------------------------------------------------------------------*/

/* This function returns the write memory address in the HPIAW register */
IDECL Uint32 HPI_getWriteAddr(void)
{
  return ( HPI_FGET(HPIAW,HPIAW));
}
/*----------------------------------------------------------------------------*/

/* This function sets the read memory address in the HPIAR register */
IDECL void HPI_setReadAddr(Uint32 address)
{
  HPI_FSET(HPIAR,HPIAR,address);
}
/*----------------------------------------------------------------------------*/

/* This function returns the read memory address in the HPIAR register */
IDECL Uint32 HPI_getReadAddr(void)
{
  return ( HPI_FGET(HPIAR,HPIAR));
}
/*----------------------------------------------------------------------------*/

#endif /* _BBU_DD_HPICSL_H_ */
/******************************************************************************\
* End of BBU_DD_HpiCsl.h
\******************************************************************************/