bbu_dd_gpiocsl.h

DSP芯片自检测程序

/*******************************************************************************
* COPYRIGHT (C)             中国普天研究院									   *
********************************************************************************
* 源文件名: BBU_DD_GpioCsl.h                                                   *
* 功能描述：Registers Description for GPIO in TMS320C6414 and TMS320C6416      *
* 编写者：Wangshiqiang                                                         *
* 版本：1.0.0                                                                  *
* 编制日期：07/14/2004                                                         *
* 说明：                                                                       *
* 修改历史：                                                                   *
*                                                                              *
*******************************************************************************/

/*------------------------------------------------------------------------------
* REGISTERS Description for GPIO in TMS320C6414 and TMS320C6416
*
* GPEN      - GPIO Enable register
* GPDIR     - GPIO Direction register 
* GPVAL     - GPIO Value register 
* GPDH      - GPIO Delta High register 
* GPHM      - GPIO High Mask register 
* GPDL      - GPIO Delta Low register 
* GPLM      - GPIO Low Mask register 
* GPGC      - GPIO Global Control register 
* GPPOL     - GPIO Interrupt Polarity register 
*
\******************************************************************************/
#ifndef _BBU_DD_GPIOCSL_H_
#define _BBU_DD_GPIOCSL_H_

#include "BBU_DD_Stdinc.h"
#include "BBU_DD_IrqCsl.h"

/******************************************************************************\
* GPIO Base Address Definitions 
\******************************************************************************/
#define GPIO_BASE_ADDR              0x01B00000u 
#define GPIO_INT_CNT                5
#define GPIO_PIN_CNT                16
/*----------------------------------------------------------------------------*/

/******************************************************************************\
*                       GPIO Enable register Definitions
*
* GPEN  -  GPIO Enable register
*
* GPxEn[15:0]    - rw, GPIO Mode enable
*
\******************************************************************************/
#define GPIO_GPEN_OFFSET            0
#define GPIO_GPEN_ADDR              0x01B00000u
#define GPIO_GPEN_DEFAULT           0x000000F9u
                                    
#define GPIO_GPEN_GPXEN_MASK        0x0000FFFFu
#define GPIO_GPEN_GPXEN_SHIFT       0x00000000u
#define GPIO_GPEN_GPXEN_DEFAULT     0x000000F9u

/******************************************************************************\
*                   GPIO Direction register Definitions
*
* GPDIR  - GPIO Direction register
*
* GPxDIR[15:0]   - rw, GPx Direction. Controls direction of GPIO pin
*
\******************************************************************************/
#define GPIO_GPDIR_OFFSET           1
#define GPIO_GPDIR_ADDR             0x01B00004u
#define GPIO_GPDIR_DEFAULT          0x00000000u
                                    
#define GPIO_GPDIR_GPXDIR_MASK      0x0000FFFFu
#define GPIO_GPDIR_GPXDIR_SHIFT     0x00000000u
#define GPIO_GPDIR_GPXDIR_DEFAULT   0x00000000u

/******************************************************************************\
*                   GPIO Value register Definitions
*
* GPVAL  - GPIO Value register
*
* GPxVAL[15:0]   - rw 
*
\******************************************************************************/
#define GPIO_GPVAL_OFFSET           2
#define GPIO_GPVAL_ADDR             0x01B00008u
#define GPIO_GPVAL_DEFAULT          0x00000000u
                                    
#define GPIO_GPVAL_GPXVAL_MASK      0x0000FFFFu
#define GPIO_GPVAL_GPXVAL_SHIFT     0x00000000u
#define GPIO_GPVAL_GPXVAL_DEFAULT   0x00000000u

/******************************************************************************\
*                    GPIO Delta High register Definitions  
*
* GPDH  - GPIO Delta High register
*  
* GPxDH[15:0]    - rw, A low-to-high transition is detected on the GPx input.
*                      Applies when the corresponding GPx pin is enabled as an
*                      input (GPxEN = 1, GPxDIR = 0)
*
\******************************************************************************/
#define GPIO_GPDH_OFFSET            4
#define GPIO_GPDH_ADDR              0x01B00010u
#define GPIO_GPDH_DEFAULT           0x00000000u
                                    
#define GPIO_GPDH_GPXDH_MASK        0x0000FFFFu
#define GPIO_GPDH_GPXDH_SHIFT       0x00000000u
#define GPIO_GPDH_GPXDH_DEFAULT     0x00000000u

/******************************************************************************\
*                    GPIO High Mask register Definitions  
*
* GPHM  - GPIO High Mask register
*
* GPxHM[15:0]    - rw, Enable interrupt/event generation based on either the
*                      corresponding GPxDH or GPxVAL bit in the GPDH and GPVAL
*                      registers. Applies when the corresponding GPxEN bit is
*                      enabled as an input(GPxEN = 1, GPxDIR = 0)
*
\******************************************************************************/
#define GPIO_GPHM_OFFSET            5
#define GPIO_GPHM_ADDR              0x01B00014u
#define GPIO_GPHM_DEFAULT           0x00000000u
                                    
#define GPIO_GPHM_GPXHM_MASK        0x0000FFFFu
#define GPIO_GPHM_GPXHM_SHIFT       0x00000000u
#define GPIO_GPHM_GPXHM_DEFAULT     0x00000000u

/******************************************************************************\
*                    GPIO Delta Low register Definitions   
*
* GPDL  - GPIO Delta Low register
*
* GPxDL[15:0]    - rw, A high-to-low transition is detected on the GPx input.
*                      Applies when the corresponding GPx pin is enabled as an
*                      input (GPxEN = 1, GPxDIR = 0)    
*
\******************************************************************************/
#define GPIO_GPDL_OFFSET            6
#define GPIO_GPDL_ADDR              0x01B00018u
#define GPIO_GPDL_DEFAULT           0x00000000u
                                    
#define GPIO_GPDL_GPXDL_MASK        0x0000FFFFu
#define GPIO_GPDL_GPXDL_SHIFT       0x00000000u
#define GPIO_GPDL_GPXDL_DEFAULT     0x00000000u

/******************************************************************************\
*                    GPIO Low Mask register Definitions  
*
* GPLM  - GPIO Low Mask register
*
* GPxLM[15:0]    - rw, Enable interrupt/event generation based on either the
*                      corresponding GPxDL or inverted GPxVAL bit in the GPDL
*                      and GPVAL registers. Applies when the corresponding
*                      GPxEN bit is enabled as an input (GPxEN = 1, GPxDIR = 0)
*
\******************************************************************************/
#define GPIO_GPLM_OFFSET            7
#define GPIO_GPLM_ADDR              0x01B0001Cu
#define GPIO_GPLM_DEFAULT           0x00000000u
                                    
#define GPIO_GPLM_GPXLM_MASK        0x0000FFFFu
#define GPIO_GPLM_GPXLM_SHIFT       0x00000000u
#define GPIO_GPLM_GPXLM_DEFAULT     0x00000000u

/******************************************************************************\
*                    GPIO Global Control register Definitions  
*
* GPGC  - GPIO Global Control register
*
* GP0M[5]        - rw, GP0 Output Mode. Applies only if GP0 is configured as an
*                      output(GP0DIR = 1 in the GPDIR register)
* GPINT0M[4]     - rw, GPINT0 interrupt/event generation mode.
* GPINTPOL[2]    - rw, GPINT Polarity. Applies to Logic Mode (GPINT0M = 1) only 
* LOGIC[1]       - rw, GPINT Logic. Applies to Logic Mode (GPINT0M = 1) only
* GPINTDV[0]     - rw, GPINT Delta/Value Mode. Applies to Logic Mode 
*                      (GPINT0M = 1) only  
*
\******************************************************************************/
#define GPIO_GPGC_OFFSET            8
#define GPIO_GPGC_ADDR              0x01B00020u
#define GPIO_GPGC_DEFAULT           0x00000000u             
           
#define GPIO_GPGC_GP0M_MASK         0x00000020u
#define GPIO_GPGC_GP0M_SHIFT        0x00000005u
#define GPIO_GPGC_GP0M_DEFAULT      0x00000000u
#define GPIO_GPGC_GP0M_GPIOMODE     0x00000000u
#define GPIO_GPGC_GP0M_LOGICMODE    0x00000001u
                                        
#define GPIO_GPGC_GPINT0M_MASK      0x00000010u
#define GPIO_GPGC_GPINT0M_SHIFT     0x00000004u
#define GPIO_GPGC_GPINT0M_DEFAULT   0x00000000u
#define GPIO_GPGC_GPINT0M_PASSMODE  0x00000000u /* based on GP0 input value */
#define GPIO_GPGC_GPINT0M_LOGICMODE 0x00000001u /* based on GPINT */
                                        
#define GPIO_GPGC_GPINTPOL_MASK         0x00000004u
#define GPIO_GPGC_GPINTPOL_SHIFT        0x00000002u
#define GPIO_GPGC_GPINTPOL_DEFAULT      0x00000000u
#define GPIO_GPGC_GPINTPOL_LOGICTRUE    0x00000000u
#define GPIO_GPGC_GPINTPOL_LOGICFALSE   0x00000001u
                                        
#define GPIO_GPGC_LOGIC_MASK        0x00000002u
#define GPIO_GPGC_LOGIC_SHIFT       0x00000001u
#define GPIO_GPGC_LOGIC_DEFAULT     0x00000000u
#define GPIO_GPGC_LOGIC_ORMODE      0x00000000u
#define GPIO_GPGC_LOGIC_ANDMODE     0x00000001u
                                        
#define GPIO_GPGC_GPINTDV_MASK      0x00000001u
#define GPIO_GPGC_GPINTDV_SHIFT     0x00000000u
#define GPIO_GPGC_GPINTDV_DEFAULT   0x00000000u
#define GPIO_GPGC_GPINTDV_DELTAMODE 0x00000000u
#define GPIO_GPGC_GPINTDV_VALUEMODE 0x00000001u
                                                                                              
/******************************************************************************\
*                    GPIO Interrupt Polarity register Definitions  
*
* GPPOL  - GPIO Interrupt Polarity register
*
* GPINTxPOL[15:0]- rw, GPINTx Polarity. Applies to Pass Through Mode only.
*
\******************************************************************************/
#define GPIO_GPPOL_OFFSET               9
#define GPIO_GPPOL_ADDR                 0x01B00024u
#define GPIO_GPPOL_DEFAULT              0x00000000u
                                        
#define GPIO_GPPOL_GPINTXPOL_MASK       0x0000FFFFu
#define GPIO_GPPOL_GPINTXPOL_SHIFT      0x00000000u
#define GPIO_GPPOL_GPINTXPOL_DEFAULT    0x00000000u
#define GPIO_GPPOL_GPINTXPOL_RISEEDGE   0x00000000u /* GPINTn is asserted high based
                                                       on a rising edge of GPn */
#define GPIO_GPPOL_GPINTXPOL_FALLEDGE   0x00000001u /* GPINTn is asserted high based
                                                       on a falling edge of GPn */

/******************************************************************************\
* GPIO Raw Registers Access Macro Definitions
\******************************************************************************/
#define GPIO_RSET(REG,x)             (*(volatile Uint32*)(GPIO_##REG##_ADDR))=((Uint32)(x))
#define GPIO_RGET(REG)               (Uint32)(*(volatile Uint32*)(GPIO_##REG##_ADDR))

#define GPIO_FSET(REG,FIELD,x)       GPIO_RSET(##REG, (GPIO_RGET(##REG) & ~GPIO_##REG##_##FIELD##_MASK) \
                                    | (((Uint32)(x) << GPIO_##REG##_##FIELD##_SHIFT) & GPIO_##REG##_##FIELD##_MASK))

#define GPIO_FGET(REG,FIELD)         (Uint32)((((Uint32)(*(volatile Uint32*)(GPIO_##REG##_ADDR))) \
                                    & GPIO_##REG##_##FIELD##_MASK) >> GPIO_##REG##_##FIELD##_SHIFT) 
/*----------------------------------------------------------------------------*/

/******************************************************************************\
*  Handle Based GPIO Parameter Macro Definitions
\******************************************************************************/
#define GPIO_ADDRH(h,REG)           (Uint32)(&(h->baseAddr[GPIO_##REG##_OFFSET])) 

#define GPIO_RSETH(h,REG,x)         (*(volatile Uint32*)(GPIO_ADDRH(h,##REG)))=((Uint32)(x))
#define GPIO_RGETH(h,REG)           (*(volatile Uint32*)(GPIO_ADDRH(h,##REG)))

#define GPIO_FSETH(h,REG,FIELD,x)   GPIO_RSETH(h,##REG, (GPIO_RGETH(h,##REG) & ~GPIO_##REG##_##FIELD##_MASK) \
                                    | (((Uint32)(x) << GPIO_##REG##_##FIELD##_SHIFT) & GPIO_##REG##_##FIELD##_MASK))

#define GPIO_FGETH(h,REG,FIELD)     (Uint32)((((Uint32)(*(volatile Uint32*)(GPIO_ADDRH(h,##REG)))) \
                                    & GPIO_##REG##_##FIELD##_MASK) >> GPIO_##REG##_##FIELD##_SHIFT) 
/*----------------------------------------------------------------------------*/

/******************************************************************************\
* GPIO Global Typedef Declarations
\******************************************************************************/
/* GPIO Port Handle Object */
typedef struct {
    Uint32          allocated;
    volatile Uint32 *baseAddr;
    Uint32          pinAllocMask;
} GPIO_Handle;

/* GPIO Port Configuration Structure */
typedef struct {
    Uint32  gpgc;
    Uint32  gpen;
    Uint32  gpdir;
    Uint32  gpval;
    Uint32  gphm;
    Uint32  gplm;   
    Uint32  gppol;
  } GPIO_Config;
/*----------------------------------------------------------------------------*/