bbu_dd_irqcsl.h

DSP芯片自检测程序

/*******************************************************************************
* COPYRIGHT (C)             中国普天研究院							           *
********************************************************************************
* 源文件名: BBU_DD_IrqCsl.h                                                    *
* 功能描述：Registers Description for EDMA in TMS320C6414 and TMS320C6416      *
* 编写者：louyajun                                                             *
* 版本：1.0.0                                                                  *
* 编制日期：07/16/2004                                                         *
* 说明：                                                                       *
* 修改历史：                                                                   *
*                                                                              *
*******************************************************************************/

/*------------------------------------------------------------------------------
* Registers Descriptions for Interrupt Selector in TMS320C6414 and TMS320C6416
*-------------------------------------------------------------------------------
* 
* MUXH   - interrupt multiplexer high register
* MUXL   - interrupt multiplexer low register
* EXTPOL - external interrupt polarity register
*
\******************************************************************************/

#ifndef _BBU_DD_IRQCSL_H_
#define _BBU_DD_IRQCSL_H_

#include "BBU_DD_Stdinc.h"
#include "BBU_DD_ChipCsl.h"

/******************************************************************************\
*              Interrupt Selector Registers Macro Definitions 
*  
* MUXH   - interrupt multiplexer high register
*
* INTSEL15[30:26] - rw, This value maps any interrupt selection number to CPU
*                       interrupt INT15
* INTSEL14[25:21] - rw, This value maps any interrupt selection number to CPU 
*                       interrupt INT14                                       
* INTSEL13[20:16] - rw, This value maps any interrupt selection number to CPU 
*                       interrupt INT13                                       
* INTSEL12[14:10] - rw, This value maps any interrupt selection number to CPU 
*                       interrupt INT12                                       
* INTSEL11[9:5]   - rw, This value maps any interrupt selection number to CPU 
*                       interrupt INT11                                       
* INTSEL10[4:0]   - rw, This value maps any interrupt selection number to CPU 
*                       interrupt INT10                                       
*
\******************************************************************************/
#define IRQ_MUXH_ADDR               0x019C0000u
#define IRQ_MUXH_DEFAULT            0x08202D43u 

#define IRQ_MUXH_INTSEL15_MASK      0x7C000000u
#define IRQ_MUXH_INTSEL15_SHIFT     0x0000001Au
#define IRQ_MUXH_INTSEL15_DEFAULT   0x00000002u

#define IRQ_MUXH_INTSEL14_MASK      0x03E00000u
#define IRQ_MUXH_INTSEL14_SHIFT     0x00000015u
#define IRQ_MUXH_INTSEL14_DEFAULT   0x00000001u

#define IRQ_MUXH_INTSEL13_MASK      0x001F0000u
#define IRQ_MUXH_INTSEL13_SHIFT     0x00000010u
#define IRQ_MUXH_INTSEL13_DEFAULT   0x00000000u

#define IRQ_MUXH_INTSEL12_MASK      0x00007C00u
#define IRQ_MUXH_INTSEL12_SHIFT     0x0000000Au
#define IRQ_MUXH_INTSEL12_DEFAULT   0x0000000Bu

#define IRQ_MUXH_INTSEL11_MASK      0x000003E0u
#define IRQ_MUXH_INTSEL11_SHIFT     0x00000005u
#define IRQ_MUXH_INTSEL11_DEFAULT   0x0000000Au

#define IRQ_MUXH_INTSEL10_MASK      0x0000001Fu
#define IRQ_MUXH_INTSEL10_SHIFT     0x00000000u
#define IRQ_MUXH_INTSEL10_DEFAULT   0x00000003u

/******************************************************************************\
*              Interrupt Selector Registers Macro Definitions 
* 
* MUXL   - interrupt multiplexer low register 
*
* INTSEL9[30:26]  - rw, This value maps any interrupt selection number to CPU
*                       interrupt INT9
* INTSEL8[25:21]  - rw, This value maps any interrupt selection number to CPU 
*                       interrupt INT8                                       
* INTSEL7[20:16]  - rw, This value maps any interrupt selection number to CPU 
*                       interrupt INT7                                       
* INTSEL6[14:10]  - rw, This value maps any interrupt selection number to CPU 
*                       interrupt INT6                                       
* INTSEL5[9:5]    - rw, This value maps any interrupt selection number to CPU 
*                       interrupt INT5                                       
* INTSEL4[4:0]    - rw, This value maps any interrupt selection number to CPU 
*                       interrupt INT4                                       
*
\******************************************************************************/
#define IRQ_MUXL_ADDR               0x019C0004u
#define IRQ_MUXL_DEFAULT            0x250718A4u 

#define IRQ_MUXL_INTSEL9_MASK       0x7C000000u
#define IRQ_MUXL_INTSEL9_SHIFT      0x0000001Au
#define IRQ_MUXL_INTSEL9_DEFAULT    0x00000009u

#define IRQ_MUXL_INTSEL8_MASK       0x03E00000u
#define IRQ_MUXL_INTSEL8_SHIFT      0x00000015u
#define IRQ_MUXL_INTSEL8_DEFAULT    0x00000008u

#define IRQ_MUXL_INTSEL7_MASK       0x001F0000u
#define IRQ_MUXL_INTSEL7_SHIFT      0x00000010u
#define IRQ_MUXL_INTSEL7_DEFAULT    0x00000007u

#define IRQ_MUXL_INTSEL6_MASK       0x00007C00u
#define IRQ_MUXL_INTSEL6_SHIFT      0x0000000Au
#define IRQ_MUXL_INTSEL6_DEFAULT    0x00000006u

#define IRQ_MUXL_INTSEL5_MASK       0x000003E0u
#define IRQ_MUXL_INTSEL5_SHIFT      0x00000005u
#define IRQ_MUXL_INTSEL5_DEFAULT    0x00000005u

#define IRQ_MUXL_INTSEL4_MASK       0x0000001Fu
#define IRQ_MUXL_INTSEL4_SHIFT      0x00000000u
#define IRQ_MUXL_INTSEL4_DEFAULT    0x00000004u

/******************************************************************************\
*              Interrupt Selector Registers Macro Definitions 
*
* EXTPOL - external interrupt polarity register 
*
* XIP  - rw
* XIPx = 1, Falling edge on an interrupt source is recognized as an interrupt
* XIPx = 0, Rising  edge on an interrupt source is recognized as an interrupt
*
\******************************************************************************/
#define IRQ_EXTPOL_ADDR             0x019C0008u
#define IRQ_EXTPOL_DEFAULT          0x00000000u

#define IRQ_EXTPOL_XIP_MASK         0x0000000Fu
#define IRQ_EXTPOL_XIP_SHIFT        0x00000000u
#define IRQ_EXTPOL_XIP_DEFAULT      0x00000000u

/******************************************************************************\
* Interrupt Selector Raw Registers Access Macro Definitions
\******************************************************************************/
#define IRQ_RSET(REG,x)             (*(volatile Uint32*)(IRQ_##REG##_ADDR))=((Uint32)(x))
#define IRQ_RGET(REG)               (Uint32)(*(volatile Uint32*)(IRQ_##REG##_ADDR))

#define IRQ_FSET(REG,FIELD,x)       IRQ_RSET(##REG, (IRQ_RGET(##REG) & ~IRQ_##REG##_##FIELD##_MASK) \
                                    | (((Uint32)(x) << IRQ_##REG##_##FIELD##_SHIFT) & IRQ_##REG##_##FIELD##_MASK))

#define IRQ_FGET(REG,FIELD)         (Uint32)((((Uint32)(*(volatile Uint32*)(IRQ_##REG##_ADDR))) \
                                    & IRQ_##REG##_##FIELD##_MASK) >> IRQ_##REG##_##FIELD##_SHIFT) 
/*----------------------------------------------------------------------------*/

/******************************************************************************\
* Interrupt Selector Global Macro Definitions
\******************************************************************************/
/* misc global settings */
#define IRQ_INT_CNT                 16
#define IRQ_EVENT_CNT               32
                                      
/* Interrupt Event ID Definitions */  
#define IRQ_EVT_DSPINT              0   /* Host port to DSP interrupt */
#define IRQ_EVT_TINT0               1   /* Timer 0 interrupt */
#define IRQ_EVT_TINT1               2   /* Timer 1 interrupt */
#define IRQ_EVT_SDINTA              3   /* EMIFA SDRAM timer interrupt */
#define IRQ_EVT_EXTINT4             4   /* External interrupt 4 */
#define IRQ_EVT_EXTINT5             5   /* External interrupt 5 */
#define IRQ_EVT_EXTINT6             6   /* External interrupt 6 */
#define IRQ_EVT_EXTINT7             7   /* External interrupt 7 */
#define IRQ_EVT_EDMAINT             8   /* EDMA channel (0-63) interrupt */
#define IRQ_EVT_XINT0               12  /* McBSP 0 transmit interrupt */
#define IRQ_EVT_RINT0               13  /* McBSP 0 receive interrupt */    
#define IRQ_EVT_XINT1               14  /* McBSP 1 transmit interrupt */   
#define IRQ_EVT_RINT1               15  /* McBSP 1 receive interrupt */    
#define IRQ_EVT_GPINT0              16  /* GPIO interrupt 0 */
#define IRQ_EVT_XINT2               17  /* McBSP 2 transmit interrupt */   
#define IRQ_EVT_RINT2               18  /* McBSP 2 receive interrupt */    
#define IRQ_EVT_TINT2               19  /* Timer 2 interrupt */
#define IRQ_EVT_SDINTB              20  /* EMIFB SDRAM timer interrupt */  
#define IRQ_EVT_PCIWAKE             21  /* PCI wakeup interrupt */
#define IRQ_EVT_UINT                23  /* UTOPIA interrupt */
#define IRQ_EVT_VCPINT              30  /* VCP interrupt */
#define IRQ_EVT_TCPINT              31  /* TCP interrupt */
#define IRQ_EVT_NA                  IRQ_EVENT_CNT

/* interrupt masks */
#define IRQ_MASK_NA                 0x00000000
#define IRQ_MASK_00                 0x00000001
#define IRQ_MASK_01                 0x00000002
#define IRQ_MASK_02                 0x00000004