bbu_dd_timercsl.h

DSP芯片自检测程序

/*******************************************************************************
* COPYRIGHT (C)             中国普天研究院									   *
********************************************************************************
* 源文件名: BBU_DD_TimerCsl.h                                                  *
* 功能描述：Registers Description for TIMER in TMS320C6414 and TMS320C6416     *
* 编写者：louyj                                                                *
* 版本：1.0.0                                                                  *
* 编制日期：07/26/2004                                                         *
* 说明：                                                                       *
* 修改历史：                                                                   *
*                                                                              *
*******************************************************************************/

/*------------------------------------------------------------------------------
* Registers Descriptions for TIMER in TMS320C6414 and TMS320C6416
*-------------------------------------------------------------------------------
*
* CTL0  - timer0 control register
* PRD0  - timer0 period register
* CNT0  - timer0 count register
*
* CTL1  - timer1 control register
* PRD1  - timer1 period register
* CNT1  - timer1 count register
*
* CTL2  - timer2 control register 
* PRD2  - timer2 period register 
* CNT2  - timer2 count register
*
\******************************************************************************/
#ifndef _BBU_DD_TIMERCSL_H_
#define _BBU_DD_TIMERCSL_H_

#include "BBU_DD_Stdinc.h"
#include "BBU_DD_IrqCsl.h"

/******************************************************************************\
* TIMER Base Address Definitions 
\******************************************************************************/
#define TIMER_DEVICE_CNT            3
#define TIMER_BASE_DEV0             0x01940000u
#define TIMER_BASE_DEV1             0x01980000u
#define TIMER_BASE_DEV2             0x01AC0000u
/*----------------------------------------------------------------------------*/

/******************************************************************************\
*                 TIMER control register Definitions
*
* CTL0  - timer0 control register
* CTL1  - timer1 control register
* CTL2  - timer2 control register
*
* SPND[15]       - rw, Suspend mode bit. Only affects operation if the clock
*                      source is internal(CLKSRC = 1). Reads always return a 0
* TSTAT[11]      - r,  Timer status bit. Value of timer output
* INVINP[10]     - rw, TINP inverter control.Only affects operation if the clock
*                      source is external(CLKSRC = 0)
* CLKSRC[9]      - rw, Timer input clock source bit
* CP[8]          - rw, Clock/pulse mode enable bit
* HLD[7]         - rw, Timer HOLD bit
* GO[6]          - rw, Timer GO bit. Resets and starts the timer counter
* PWID[4]        - rw, Pulse width bit. Only used in pulse mode (CP = 0)
* DATIN[3]       - r,  Data in bit. Value on TINP pin
* DATOUT[2]      - rw, Data output bit. Used only if FUNC = 0
* INVOUT[1]      - rw, TOUT inverter control bit. Used only if FUNC = 1
* FUNC[0]        - rw, Function of TOUT pin
*
\******************************************************************************/
#define TIMER_CTL_OFFSET            0                                  
#define TIMER_CTL0_ADDR             0x01940000u
#define TIMER_CTL1_ADDR             0x01980000u
#define TIMER_CTL2_ADDR             0x01AC0000u
#define TIMER_CTL_DEFAULT           0x00000000u

#define TIMER_CTL_SPND_MASK         0x00008000u
#define TIMER_CTL_SPND_SHIFT        0x0000000Fu
#define TIMER_CTL_SPND_DEFAULT      0x00000000u
#define TIMER_CTL_SPND_NO           0x00000000u /* Timer continues counting 
                                                   during an emulation halt.*/
#define TIMER_CTL_SPND_YES          0x00000001u /* Timer stops counting during
                                                   an emulation halt. */
                                    
#define TIMER_CTL_TSTAT_MASK        0x00000800u
#define TIMER_CTL_TSTAT_SHIFT       0x0000000Bu
#define TIMER_CTL_TSTAT_DEFAULT     0x00000000u
#define TIMER_CTL_TSTAT_0           0x00000000u
#define TIMER_CTL_TSTAT_1           0x00000001u
                                    
#define TIMER_CTL_INVINP_MASK       0x00000400u
#define TIMER_CTL_INVINP_SHIFT      0x0000000Au
#define TIMER_CTL_INVINP_DEFAULT    0x00000000u
#define TIMER_CTL_INVINP_NO         0x00000000u /* Uninverting TINP */
#define TIMER_CTL_INVINP_YES        0x00000001u /* Inverting TINP */
                                    
#define TIMER_CTL_CLKSRC_MASK       0x00000200u
#define TIMER_CTL_CLKSRC_SHIFT      0x00000009u
#define TIMER_CTL_CLKSRC_DEFAULT    0x00000000u
#define TIMER_CTL_CLKSRC_EXTERNAL   0x00000000u /* External clock source drives 
                                                   the TINP pin */
#define TIMER_CTL_CLKSRC_CPUOVR8    0x00000001u /* Internal clock source,
                                                   CPU clock/8 */
                                    
#define TIMER_CTL_CP_MASK           0x00000100u
#define TIMER_CTL_CP_SHIFT          0x00000008u
#define TIMER_CTL_CP_DEFAULT        0x00000000u
#define TIMER_CTL_CP_PULSE          0x00000000u
#define TIMER_CTL_CP_CLOCK          0x00000001u
                                    
#define TIMER_CTL_HLD_MASK          0x00000080u
#define TIMER_CTL_HLD_SHIFT         0x00000007u
#define TIMER_CTL_HLD_DEFAULT       0x00000000u
#define TIMER_CTL_HLD_YES           0x00000000u /* Counter is disabled and 
                                                   held in the current state */
#define TIMER_CTL_HLD_NO            0x00000001u /* Counter is allowed to count*/

#define TIMER_CTL_GO_MASK           0x00000040u
#define TIMER_CTL_GO_SHIFT          0x00000006u
#define TIMER_CTL_GO_DEFAULT        0x00000000u
#define TIMER_CTL_GO_NO             0x00000000u /*  No effect on the timers. */
#define TIMER_CTL_GO_YES            0x00000001u 
                                    
#define TIMER_CTL_PWID_MASK         0x00000010u
#define TIMER_CTL_PWID_SHIFT        0x00000004u
#define TIMER_CTL_PWID_DEFAULT      0x00000000u
#define TIMER_CTL_PWID_ONE          0x00000000u
#define TIMER_CTL_PWID_TWO          0x00000001u
                                    
#define TIMER_CTL_DATIN_MASK        0x00000008u
#define TIMER_CTL_DATIN_SHIFT       0x00000003u
#define TIMER_CTL_DATIN_DEFAULT     0x00000000u
#define TIMER_CTL_DATIN_0           0x00000000u
#define TIMER_CTL_DATIN_1           0x00000001u
                                    
#define TIMER_CTL_DATOUT_MASK       0x00000004u
#define TIMER_CTL_DATOUT_SHIFT      0x00000002u
#define TIMER_CTL_DATOUT_DEFAULT    0x00000000u
#define TIMER_CTL_DATOUT_0          0x00000000u
#define TIMER_CTL_DATOUT_1          0x00000001u
                                    
#define TIMER_CTL_INVOUT_MASK       0x00000002u
#define TIMER_CTL_INVOUT_SHIFT      0x00000001u
#define TIMER_CTL_INVOUT_DEFAULT    0x00000000u
#define TIMER_CTL_INVOUT_NO         0x00000000u /* Uninverted TSTAT drives TOUT */
#define TIMER_CTL_INVOUT_YES        0x00000001u /* Inverted TSTAT drives TOUT */
                                    
#define TIMER_CTL_FUNC_MASK         0x00000001u
#define TIMER_CTL_FUNC_SHIFT        0x00000000u
#define TIMER_CTL_FUNC_DEFAULT      0x00000000u
#define TIMER_CTL_FUNC_GPIO         0x00000000u
#define TIMER_CTL_FUNC_TOUT         0x00000001u  

/******************************************************************************\
*                 TIMER period register Definitions
*
* PRD0  - timer0 period register
* PRD1  - timer1 period register
* PRD2  - timer2 period register 
*
* PRD            - rw, The timer period register contains the number of timer
*                      input clock cycles to count 
*
\******************************************************************************/
#define TIMER_PRD_OFFSET            1
#define TIMER_PRD0_ADDR             0x01940004u
#define TIMER_PRD1_ADDR             0x01980004u
#define TIMER_PRD2_ADDR             0x01AC0004u
#define TIMER_PRD_DEFAULT           0x00000000u                                  
                                    
#define TIMER_PRD_PRD_MASK          0xFFFFFFFFu
#define TIMER_PRD_PRD_SHIFT         0x00000000u
#define TIMER_PRD_PRD_DEFAULT       0x00000000u

/******************************************************************************\
*                 TIMER count register Definitions
*
* CNT0  - timer0 count register
* CNT1  - timer1 count register
* CNT2  - timer2 count register
*
* CNT            - rw, The timer counter register increments when it is enabled
*                      to count