📄 bbu_dd_edmacsl.h
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#define EDMA_CHA_LINK10 74 /* System link channel10 */
#define EDMA_CHA_LINK11 75 /* System link channel11 */
#define EDMA_CHA_LINK12 76 /* System link channel12 */
#define EDMA_CHA_LINK13 77 /* System link channel13 */
#define EDMA_CHA_LINK14 78 /* System link channel14 */
#define EDMA_CHA_LINK15 79 /* System link channel15 */
#define EDMA_CHA_LINK16 80 /* System link channel16 */
#define EDMA_CHA_LINK17 81 /* System link channel17 */
#define EDMA_CHA_LINK18 82 /* System link channel18 */
#define EDMA_CHA_LINK19 83 /* System link channel19 */
#define EDMA_CHA_LINK20 84 /* System link channel20 */
#define EDMA_CHA_LINK21 16 /* User defined link channel21 */
#define EDMA_CHA_LINK22 33 /* User defined link channel22 */
#define EDMA_CHA_LINK23 34 /* User defined link channel23 */
#define EDMA_CHA_LINK24 35 /* User defined link channel24 */
#define EDMA_CHA_LINK25 36 /* User defined link channel25 */
#define EDMA_CHA_LINK26 37 /* User defined link channel26 */
#define EDMA_CHA_LINK27 38 /* User defined link channel27 */
#define EDMA_CHA_LINK28 39 /* User defined link channel28 */
#define EDMA_CHA_LINK29 41 /* User defined link channel29 */
#define EDMA_CHA_LINK30 42 /* User defined link channel30 */
#define EDMA_CHA_LINK31 43 /* User defined link channel31 */
#define EDMA_CHA_LINK32 44 /* User defined link channel32 */
#define EDMA_CHA_LINK33 45 /* User defined link channel33 */
#define EDMA_CHA_LINK34 46 /* User defined link channel34 */
#define EDMA_CHA_LINK35 47 /* User defined link channel35 */
#define EDMA_CHA_LINK36 56 /* User defined link channel36 */
#define EDMA_CHA_LINK37 57 /* User defined link channel37 */
#define EDMA_CHA_LINK38 58 /* User defined link channel38 */
#define EDMA_CHA_LINK39 59 /* User defined link channel39 */
#define EDMA_CHA_LINK40 60 /* User defined link channel40 */
#define EDMA_CHA_LINK41 61 /* User defined link channel41 */
#define EDMA_CHA_LINK42 62 /* User defined link channel42 */
#define EDMA_CHA_LINK43 63 /* User defined link channel43 */
/* EDMA Priority Queues and Length */
#define EDMA_Q0 0
#define EDMA_Q1 1
#define EDMA_Q2 2
#define EDMA_Q3 3
#define EDMA_Q0_LEN 0x00000001u
#define EDMA_Q1_LEN 0x00000001u
#define EDMA_Q2_LEN 0x00000006u
#define EDMA_Q3_LEN 0x00000006u
/* EDMA Transfer Types */
#define EDMA_TYPE_C 0x80000000 /* Normal EDMA Handle */
#define EDMA_TYPE_T 0x40000000 /* Link EDMA Handle */
/* EDMA Parameter Macro Definitions */
#define EDMA_CHA_CNT 64
#define EDMA_PRAM_START 0x01A00000u
#define EDMA_PRAM_SIZE 0x00000800u
#define EDMA_ENTRY_SIZE 0x00000018u
#define EDMA_LINK_CNT 85
#define EDMA_NULL_HANDLE 0x40400600u
/* EDMA Event Polarity */
#define EDMA_EVT_LOWHIGH 0 /* Rising Edge */
#define EDMA_EVT_HIGHLOW 1 /* Falling Edge */
/* EDMA Chaining Flag */
#define EDMA_TCC_SET 1
#define EDMA_ATCC_SET 2
/* EDMA Channel Priority definitions */
#define EDMA_MCBSP0X_PRI 0x00000003u
#define EDMA_MCBSP1X_PRI 0x00000003u
#define EDMA_MCBSP2X_PRI 0x00000003u
#define EDMA_MCBSP0R_PRI 0x00000002u
#define EDMA_MCBSP1R_PRI 0x00000002u
#define EDMA_MCBSP2R_PRI 0x00000002u
#define EDMA_EMIFA_WRITE_DPRAM_PRI 0x00000003u
#define EDMA_EMIFA_READ_DPRAM_PRI 0x00000002u
#define EDMA_EMIFA_WRITE_SDRAM_PRI 0x00000003u
#define EDMA_EMIFA_READ_SDRAM_PRI 0x00000002u
#define EDMA_TCPX_PRI 0x00000003u
#define EDMA_TCPR_PRI 0x00000002u
#define EDMA_VCPX_PRI 0x00000003u
#define EDMA_VCPR_PRI 0x00000002u
/*----------------------------------------------------------------------------*/
/******************************************************************************\
* EDMA Inline Function Declarations
\******************************************************************************/
IDECL Uint32 EDMA_getPriQStatus(void);
IDECL void EDMA_resetPriQLength(Sint32 priNum);
IDECL void EDMA_setPriQLength(Sint32 priNum, Sint32 length);
IDECL void EDMA_enableChannel(EDMA_Handle hEdma);
IDECL void EDMA_disableChannel(EDMA_Handle hEdma);
IDECL void EDMA_setChannel(EDMA_Handle hEdma);
IDECL Uint32 EDMA_getChannel(EDMA_Handle hEdma);
IDECL void EDMA_clearChannel(EDMA_Handle hEdma);
IDECL void EDMA_setEvtPolarity(EDMA_Handle hEdma,Sint32 polarity);
IDECL void EDMA_enableChaining(EDMA_Handle hEdma);
IDECL void EDMA_disableChaining(EDMA_Handle hEdma);
IDECL void EDMA_link(EDMA_Handle parent, EDMA_Handle child);
/******************************************************************************\
* EDMA Inline Function Definitions
\******************************************************************************/
/* Get Status of Priority Queue */
IDECL Uint32 EDMA_getPriQStatus(void)
{
return EDMA_RGET(PQSR);
}
/*----------------------------------------------------------------------------*/
/* Priority Queue Length is Set to Default */
IDECL void EDMA_resetPriQLength(Sint32 priNum)
{
Uint32 gie;
gie = IRQ_globalDisable();
switch (priNum)
{
case 0x0: EDMA_RSET(PQAR0,EDMA_PQAR0_PQA_DEFAULT);
break;
case 0x1: EDMA_RSET(PQAR1,EDMA_PQAR1_PQA_DEFAULT);
break;
case 0x2: EDMA_RSET(PQAR2,EDMA_PQAR2_PQA_DEFAULT);
break;
case 0x3: EDMA_RSET(PQAR3,EDMA_PQAR3_PQA_DEFAULT);
break;
}
IRQ_globalRestore(gie);
}
/*----------------------------------------------------------------------------*/
/* Set Priority Queue Length */
IDECL void EDMA_setPriQLength(Sint32 priNum, Sint32 length)
{
Uint32 gie;
gie = IRQ_globalDisable();
switch (priNum)
{
case 0x0: EDMA_RSET(PQAR0,(EDMA_PQAR0_PQA_MASK & length));
break;
case 0x1: EDMA_RSET(PQAR1,(EDMA_PQAR1_PQA_MASK & length));
break;
case 0x2: EDMA_RSET(PQAR2,(EDMA_PQAR2_PQA_MASK & length));
break;
case 0x3: EDMA_RSET(PQAR3,(EDMA_PQAR3_PQA_MASK & length));
break;
}
IRQ_globalRestore(gie);
}
/*----------------------------------------------------------------------------*/
/* Set EDMA Event Enable Register to Enable a EDMA Channel */
IDECL void EDMA_enableChannel(EDMA_Handle hEdma)
{
Uint32 gie;
Sint32 chaNum;
gie = IRQ_globalDisable();
chaNum = (hEdma & 0x00FF0000)>>16;
if((chaNum>=0) && (chaNum<32))
{
EDMA_RSET(EERL,EDMA_RGET(EERL) | (1<<chaNum));
}
if((chaNum>=32) && (chaNum<EDMA_CHA_CNT))
{
EDMA_RSET(EERH,EDMA_RGET(EERH) | (1<<(chaNum-32)));
}
IRQ_globalRestore(gie);
}
/*----------------------------------------------------------------------------*/
/* Clear EDMA Event Enable Register to Disable a EDMA Channel */
IDECL void EDMA_disableChannel(EDMA_Handle hEdma)
{
Uint32 gie;
Sint32 chaNum;
gie = IRQ_globalDisable();
chaNum = (hEdma & 0x00FF0000)>>16;
if((chaNum>=0) && (chaNum<32))
{
EDMA_RSET(EERL,EDMA_RGET(EERL) & ~(1<<chaNum));
}
if((chaNum>=32) && (chaNum<EDMA_CHA_CNT))
{
EDMA_RSET(EERH,EDMA_RGET(EERH) & ~(1<<(chaNum-32)));
}
IRQ_globalRestore(gie);
}
/*----------------------------------------------------------------------------*/
/* Set EDMA Event Set Register to Trigger off a EDMA Transfer */
IDECL void EDMA_setChannel(EDMA_Handle hEdma)
{
Uint32 gie;
Sint32 chaNum;
gie = IRQ_globalDisable();
chaNum = (hEdma & 0x00FF0000)>>16;
if((chaNum>=0) && (chaNum<32))
{
EDMA_RSET(ESRL,EDMA_RGET(ESRL) | (1<<chaNum));
}
if((chaNum>=32) && (chaNum<EDMA_CHA_CNT))
{
EDMA_RSET(ESRH,EDMA_RGET(ESRH) | (1<<(chaNum-32)));
}
IRQ_globalRestore(gie);
}
/*----------------------------------------------------------------------------*/
/* get EDMA Event Register Status */
/* Return Value = 0,There is no Event */
/* Return Value = 1,There is Event */
IDECL Uint32 EDMA_getChannel(EDMA_Handle hEdma)
{
Uint32 gie;
Sint32 chaNum;
Uint32 result;
gie = IRQ_globalDisable();
chaNum = (hEdma & 0x00FF0000)>>16;
if((chaNum>=0) && (chaNum<32))
{
result = (Uint32)((EDMA_RGET(ERL) & (1<<chaNum)) ? 1 : 0);
}
if((chaNum>=32) && (chaNum<EDMA_CHA_CNT))
{
result = (Uint32)((EDMA_RGET(ERH) & (1<<(chaNum-32))) ? 1 : 0);
}
IRQ_globalRestore(gie);
return result;
}
/*----------------------------------------------------------------------------*/
/* Set EDMA Event Clear Register to Clear a Event */
IDECL void EDMA_clearChannel(EDMA_Handle hEdma)
{
Uint32 gie;
Sint32 chaNum;
gie = IRQ_globalDisable();
chaNum = (hEdma & 0x00FF0000)>>16;
if((chaNum>=0) && (chaNum<32))
{
EDMA_RSET(ECRL,1<<chaNum);
}
if((chaNum>=32) && (chaNum<EDMA_CHA_CNT))
{
EDMA_RSET(ECRH,1<<(chaNum-32));
}
IRQ_globalRestore(gie);
}
/*----------------------------------------------------------------------------*/
/* Set EDMA Event Polarity */
IDECL void EDMA_setEvtPolarity(EDMA_Handle hEdma,Sint32 polarity)
{
Uint32 gie;
Sint32 chaNum;
gie = IRQ_globalDisable();
chaNum = (hEdma & 0x00FF0000)>>16;
if((chaNum>=0) && (chaNum<32))
{
EDMA_RSET(EPRL,(EDMA_RGET(EPRL) & ~(1<<chaNum)) | (polarity<<chaNum));
}
if((chaNum>=32) && (chaNum<EDMA_CHA_CNT))
{
EDMA_RSET(EPRH,(EDMA_RGET(EPRH) & ~(1<<(chaNum-32))) | (polarity<<(chaNum-32)));
}
IRQ_globalRestore(gie);
}
/*----------------------------------------------------------------------------*/
/* Enables Channel Chaining Enable Register associated with the EDMA handle */
/* the EDMA Channel is Chained to parent Channel */
IDECL void EDMA_enableChaining(EDMA_Handle hEdma)
{
Uint32 gie;
Sint32 chaNum;
gie = IRQ_globalDisable();
chaNum = (hEdma & 0x00FF0000)>>16;
if((chaNum>=0) && (chaNum<32))
{
EDMA_RSET(CCERL,EDMA_RGET(CCERL) | (1<<chaNum));
}
if((chaNum>=32) && (chaNum<EDMA_CHA_CNT))
{
EDMA_RSET(CCERH,EDMA_RGET(CCERH) | (1<<(chaNum-32)));
}
IRQ_globalRestore(gie);
}
/*----------------------------------------------------------------------------*/
/* Clear Channel Chaining Enable Register associated with the EDMA handle */
IDECL void EDMA_disableChaining(EDMA_Handle hEdma)
{
Uint32 gie;
Sint32 chaNum;
gie = IRQ_globalDisable();
chaNum = (hEdma & 0x00FF0000)>>16;
if((chaNum>=0) && (chaNum<32))
{
EDMA_RSET(CCERL,EDMA_RGET(CCERL) & ~(1<<chaNum));
}
if((chaNum>=32) && (chaNum<EDMA_CHA_CNT))
{
EDMA_RSET(CCERH,EDMA_RGET(CCERH) & ~(1<<(chaNum-32)));
}
IRQ_globalRestore(gie);
}
/*----------------------------------------------------------------------------*/
/* Links Two EDMA Transfers together by Setting LINK Field of Parent Channel */
IDECL void EDMA_link(EDMA_Handle parent, EDMA_Handle child)
{
EDMA_FSETH(parent,RLD,LINK,child);
}
/*----------------------------------------------------------------------------*/
#endif /* _BBU_DD_EDMACSL_H_ */
/******************************************************************************\
* End of BBU_DD_EdmaCsl.h
\******************************************************************************/
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