📄 bbu_dd_edmacsl.h
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#define QDMA_QSRC_SRC_SHIFT 0x00000000u
#define QDMA_QSRC_SRC_DEFAULT 0x00000000u
/******************************************************************************\
* QDMA Registers Macro Definitions
*
* QCNT - QDMA transfer count register
*
* FRMCNT[31:16] - rw, FRMCNT + 1 specifies the number of frames in a 1D block
* or number of arrays in a 2D block
* ELECNT[15:0] - rw, ELECNT specifies the number of elements in a frame
* or an array
*
\******************************************************************************/
#define QDMA_QCNT_ADDR 0x02000008u
#define QDMA_QCNT_DEFAULT 0x00000000u
#define QDMA_QCNT_FRMCNT_MASK 0xFFFF0000u
#define QDMA_QCNT_FRMCNT_SHIFT 0x00000010u
#define QDMA_QCNT_FRMCNT_DEFAULT 0x00000000u
#define QDMA_QCNT_ELECNT_MASK 0x0000FFFFu
#define QDMA_QCNT_ELECNT_SHIFT 0x00000000u
#define QDMA_QCNT_ELECNT_DEFAULT 0x00000000u
/******************************************************************************\
* QDMA Registers Macro Definitions
*
* QDST - QDMA destination address register
*
* DST[31:0] - rw,specifies the starting byte address of the destination
*
\******************************************************************************/
#define QDMA_QDST_ADDR 0x0200000Cu
#define QDMA_QDST_DEFAULT 0x00000000u
#define QDMA_QDST_DST_MASK 0xFFFFFFFFu
#define QDMA_QDST_DST_SHIFT 0x00000000u
#define QDMA_QDST_DST_DEFAULT 0x00000000u
/******************************************************************************\
* QDMA Registers Macro Definitions
*
* QIDX - QDMA index register
*
* FRMIDX[31:16] - rw, frame or array index bits
* ELEIDX[15:0] - rw, element index bits
*
\******************************************************************************/
#define QDMA_QIDX_ADDR 0x02000010u
#define QDMA_QIDX_DEFAULT 0x00000000u
#define QDMA_QIDX_FRMIDX_MASK 0xFFFF0000u
#define QDMA_QIDX_FRMIDX_SHIFT 0x00000010u
#define QDMA_QIDX_FRMIDX_DEFAULT 0x00000000u
#define QDMA_QIDX_ELEIDX_MASK 0x0000FFFFu
#define QDMA_QIDX_ELEIDX_SHIFT 0x00000000u
#define QDMA_QIDX_ELEIDX_DEFAULT 0x00000000u
/******************************************************************************\
* QDMA Registers Macro Definitions
*
* QSOPT - QDMA options pseudo register
*
* PRI[31:29] - rw, priority levels for QDMA
* ESIZE[28:27] - rw, element size bits
* 2DS[26] - rw, source dimension bit
* SUM[25:24] - rw, source address update mode bits
* 2DD[23] - rw, destination dimension bit
* DUM[22:21] - rw, destination address update mode bits
* TCINT[20] - rw, transfer complete interrupt bit
* TCC[19:16] - rw, transfer complete code bits
* TCCM[14:13] - rw, transfer complete code most-significant bits
* FS[0] - rw, frame synchronization bit
*
\******************************************************************************/
#define QDMA_QSOPT_ADDR 0x02000020u
#define QDMA_QSOPT_DEFAULT 0x00000000u
#define QDMA_QSOPT_PRI_MASK 0xE0000000u
#define QDMA_QSOPT_PRI_SHIFT 0x0000001Du
#define QDMA_QSOPT_PRI_DEFAULT 0x00000000u
#define QDMA_QSOPT_PRI_URGENT 0x00000000u
#define QDMA_QSOPT_PRI_HIGH 0x00000001u
#define QDMA_QSOPT_PRI_MEDIUM 0x00000002u
#define QDMA_QSOPT_PRI_LOW 0x00000003u
#define QDMA_QSOPT_ESIZE_MASK 0x18000000u
#define QDMA_QSOPT_ESIZE_SHIFT 0x0000001Bu
#define QDMA_QSOPT_ESIZE_DEFAULT 0x00000000u
#define QDMA_QSOPT_ESIZE_32BIT 0x00000000u
#define QDMA_QSOPT_ESIZE_16BIT 0x00000001u
#define QDMA_QSOPT_ESIZE_8BIT 0x10000002u
#define QDMA_QSOPT_2DS_MASK 0x04000000u
#define QDMA_QSOPT_2DS_SHIFT 0x0000001Au
#define QDMA_QSOPT_2DS_DEFAULT 0x00000000u
#define QDMA_QSOPT_2DS_NO 0x00000000u
#define QDMA_QSOPT_2DS_YES 0x00000001u
#define QDMA_QSOPT_SUM_MASK 0x03000000u
#define QDMA_QSOPT_SUM_SHIFT 0x00000018u
#define QDMA_QSOPT_SUM_DEFAULT 0x00000000u
#define QDMA_QSOPT_SUM_NONE 0x00000000u
#define QDMA_QSOPT_SUM_INC 0x00000001u
#define QDMA_QSOPT_SUM_DEC 0x00000002u
#define QDMA_QSOPT_SUM_IDX 0x00000003u
#define QDMA_QSOPT_2DD_MASK 0x00800000u
#define QDMA_QSOPT_2DD_SHIFT 0x00000017u
#define QDMA_QSOPT_2DD_DEFAULT 0x00000000u
#define QDMA_QSOPT_2DD_NO 0x00000000u
#define QDMA_QSOPT_2DD_YES 0x00000001u
#define QDMA_QSOPT_DUM_MASK 0x00600000u
#define QDMA_QSOPT_DUM_SHIFT 0x00000015u
#define QDMA_QSOPT_DUM_DEFAULT 0x00000000u
#define QDMA_QSOPT_DUM_NONE 0x00000000u
#define QDMA_QSOPT_DUM_INC 0x00000001u
#define QDMA_QSOPT_DUM_DEC 0x00000002u
#define QDMA_QSOPT_DUM_IDX 0x00000003u
#define QDMA_QSOPT_TCINT_MASK 0x00100000u
#define QDMA_QSOPT_TCINT_SHIFT 0x00000014u
#define QDMA_QSOPT_TCINT_DEFAULT 0x00000000u
#define QDMA_QSOPT_TCINT_NO 0x00000000u
#define QDMA_QSOPT_TCINT_YES 0x00000001u
#define QDMA_QSOPT_TCC_MASK 0x000F0000u
#define QDMA_QSOPT_TCC_SHIFT 0x00000010u
#define QDMA_QSOPT_TCC_DEFAULT 0x00000000u
#define QDMA_QSOPT_TCCM_MASK 0x00006000u
#define QDMA_QSOPT_TCCM_SHIFT 0x0000000Du
#define QDMA_QSOPT_TCCM_DEFAULT 0x00000000u
#define QDMA_QSOPT_FS_MASK 0x00000001u
#define QDMA_QSOPT_FS_SHIFT 0x00000000u
#define QDMA_QSOPT_FS_DEFAULT 0x00000000u
#define QDMA_QSOPT_FS_NO 0x00000000u
#define QDMA_QSOPT_FS_YES 0x00000001u
/******************************************************************************\
* QDMA Registers Macro Definitions
*
* QSSRC - QDMA source address pseudo register
*
* SRC[31:0] - rw, specifies the starting byte address of the source
*
\******************************************************************************/
#define QDMA_QSSRC_ADDR 0x02000024u
#define QDMA_QSSRC_DEFAULT 0x00000000u
#define QDMA_QSSRC_SRC_MASK 0xFFFFFFFFu
#define QDMA_QSSRC_SRC_SHIFT 0x00000000u
#define QDMA_QSSRC_SRC_DEFAULT 0x00000000u
/******************************************************************************\
* QDMA Registers Macro Definitions
*
* QSCNT - QDMA transfer count pseudo register
*
* FRMCNT[31:16] - rw, FRMCNT + 1 specifies the number of frames in a 1D block
* or number of arrays in a 2D block
* ELECNT[15:0] - rw, ELECNT specifies the number of elements in a frame
* or an array
*
\******************************************************************************/
#define QDMA_QSCNT_ADDR 0x02000028u
#define QDMA_QSCNT_DEFAULT 0x00000000u
#define QDMA_QSCNT_FRMCNT_MASK 0xFFFF0000u
#define QDMA_QSCNT_FRMCNT_SHIFT 0x00000010u
#define QDMA_QSCNT_FRMCNT_DEFAULT 0x00000000u
#define QDMA_QSCNT_ELECNT_MASK 0x0000FFFFu
#define QDMA_QSCNT_ELECNT_SHIFT 0x00000000u
#define QDMA_QSCNT_ELECNT_DEFAULT 0x00000000u
/******************************************************************************\
* QDMA Registers Macro Definitions
*
* QSDST - QDMA destination address pseudo register
*
* DST[31:0] - rw,specifies the starting byte address of the destination
*
\******************************************************************************/
#define QDMA_QSDST_ADDR 0x0200002Cu
#define QDMA_QSDST_DEFAULT 0x00000000u
#define QDMA_QSDST_DST_MASK 0xFFFFFFFFu
#define QDMA_QSDST_DST_SHIFT 0x00000000u
#define QDMA_QSDST_DST_DEFAULT 0x00000000u
/******************************************************************************\
* QDMA Registers Macro Definitions
*
* QSIDX - QDMA index pseudo register
*
* FRMIDX[31:16] - rw, frame or array index bits
* ELEIDX[15:0] - rw, element index bits
*
\******************************************************************************/
#define QDMA_QSIDX_ADDR 0x02000030u
#define QDMA_QSIDX_DEFAULT 0x00000000u
#define QDMA_QSIDX_FRMIDX_MASK 0xFFFF0000u
#define QDMA_QSIDX_FRMIDX_SHIFT 0x00000010u
#define QDMA_QSIDX_FRMIDX_DEFAULT 0x00000000u
#define QDMA_QSIDX_ELEIDX_MASK 0x0000FFFFu
#define QDMA_QSIDX_ELEIDX_SHIFT 0x00000000u
#define QDMA_QSIDX_ELEIDX_DEFAULT 0x00000000u
/******************************************************************************\
* QDMA Raw Registers Access Macro Definitions
\******************************************************************************/
#define QDMA_RSET(REG,x) (*(volatile Uint32*)(QDMA_##REG##_ADDR))=((Uint32)(x))
#define QDMA_RGET(REG) (Uint32)(*(volatile Uint32*)(QDMA_##REG##_ADDR))
#define QDMA_FSET(REG,FIELD,x) QDMA_RSET(##REG, (QDMA_RGET(##REG) & ~QDMA_##REG##_##FIELD##_MASK) \
| (((Uint32)(x) << QDMA_##REG##_##FIELD##_SHIFT) & QDMA_##REG##_##FIELD##_MASK))
#define QDMA_FGET(REG,FIELD) (Uint32)((((Uint32)(*(volatile Uint32*)(QDMA_##REG##_ADDR))) \
& QDMA_##REG##_##FIELD##_MASK) >> QDMA_##REG##_##FIELD##_SHIFT)
/*----------------------------------------------------------------------------*/
/******************************************************************************\
* EDMA Global Typedef Declarations
\******************************************************************************/
typedef struct
{
Uint32 opt;
Uint32 src;
Uint32 cnt;
Uint32 dst;
Uint32 idx;
Uint32 rld;
} EDMA_ParaConfig;
typedef Uint32 EDMA_Handle;
/*----------------------------------------------------------------------------*/
/******************************************************************************\
* EDMA Global Macro Definitions
\******************************************************************************/
/* The Mapping between EDMA Channels and Events */
#define EDMA_CHA_DSPINT 0 /* Host Port to DSP Interrupt */
#define EDMA_CHA_TINT0 1 /* Timer0 Interrupt */
#define EDMA_CHA_TINT1 2 /* Timer1 Interrupt */
#define EDMA_CHA_SDINT 3 /* EMIFA SDRAM timer interrupt */
#define EDMA_CHA_EXTINT4 4 /* External Interrupt 4 */
#define EDMA_CHA_EXTINT5 5 /* External Interrupt 5 */
#define EDMA_CHA_EXTINT6 6 /* External Interrupt 6 */
#define EDMA_CHA_EXTINT7 7 /* External Interrupt 7 */
#define EDMA_CHA_GPINT0 8 /* GPIO event 0 */
#define EDMA_CHA_GPINT1 9 /* GPIO event 1 */
#define EDMA_CHA_GPINT2 10 /* GPIO event 2 */
#define EDMA_CHA_GPINT3 11 /* GPIO event 3 */
#define EDMA_CHA_XEVT0 12 /* McBSP0 Transmit Event */
#define EDMA_CHA_REVT0 13 /* McBSP0 Receive Event */
#define EDMA_CHA_XEVT1 14 /* McBSP1 Transmit Event */
#define EDMA_CHA_REVT1 15 /* McBSP1 Receive Event */
#define EDMA_CHA_XEVT2 17 /* McBSP2 Transmit Event */
#define EDMA_CHA_REVT2 18 /* McBSP2 Receive Event */
#define EDMA_CHA_TINT2 19 /* Timer2 Interrupt */
#define EDMA_CHA_SDINTB 20 /* EMIFB SDRAM timer interrupt*/
#define EDMA_CHA_PCI 21 /* PCI wakeup interrupt*/
#define EDMA_CHA_CPU1 22 /* CPU trigger1 */
#define EDMA_CHA_CPU2 23 /* CPU trigger2 */
#define EDMA_CHA_CPU3 24 /* CPU trigger3 */
#define EDMA_CHA_CPU4 25 /* CPU trigger4 */
#define EDMA_CHA_CPU5 26 /* CPU trigger5 */
#define EDMA_CHA_CPU6 27 /* CPU trigger6 */
#define EDMA_CHA_VCPREVT 28 /* VCP Receive Interrupt */
#define EDMA_CHA_VCPXEVT 29 /* VCP Transmit Interrupt */
#define EDMA_CHA_TCPREVT 30 /* TCP Receive Interrupt */
#define EDMA_CHA_TCPXEVT 31 /* TCP transmit Interrupt */
#define EDMA_CHA_UREVT 32 /* UTOPIA receive event */
#define EDMA_CHA_UXEVT 40 /* UTOPIA transmit event */
#define EDMA_CHA_GPINT8 48 /* GPIO event 8 */
#define EDMA_CHA_GPINT9 49 /* GPIO event 9 */
#define EDMA_CHA_GPINT10 50 /* GPIO event 10 */
#define EDMA_CHA_GPINT11 51 /* GPIO event 11 */
#define EDMA_CHA_GPINT12 52 /* GPIO event 12 */
#define EDMA_CHA_GPINT13 53 /* GPIO event 13 */
#define EDMA_CHA_GPINT14 54 /* GPIO event 14 */
#define EDMA_CHA_GPINT15 55 /* GPIO event 15 */
#define EDMA_CHA_CHAIN1 56 /* Chain Channel1 */
#define EDMA_CHA_CHAIN2 57 /* Chain Channel2 */
#define EDMA_CHA_CHAIN3 58 /* Chain Channel3 */
#define EDMA_CHA_CHAIN4 59 /* Chain Channel4 */
#define EDMA_CHA_CHAIN5 60 /* Chain Channel5 */
#define EDMA_CHA_CHAIN6 61 /* Chain Channel6 */
#define EDMA_CHA_CHAIN7 62 /* Chain Channel7 */
#define EDMA_CHA_CHAIN8 63 /* Chain Channel8 */
/* The Mapping between EDMA Channels and TCC */
#define EDMA_TCC_DSPINT 0
#define EDMA_TCC_TINT0 1
#define EDMA_TCC_TINT1 2
#define EDMA_TCC_SDINT 3
#define EDMA_TCC_EXTINT4 4
#define EDMA_TCC_EXTINT5 5
#define EDMA_TCC_EXTINT6 6
#define EDMA_TCC_EXTINT7 7
#define EDMA_TCC_GPINT0 8
#define EDMA_TCC_GPINT1 9
#define EDMA_TCC_GPINT2 10
#define EDMA_TCC_GPINT3 11
#define EDMA_TCC_XEVT0 12
#define EDMA_TCC_REVT0 13
#define EDMA_TCC_XEVT1 14
#define EDMA_TCC_REVT1 15
#define EDMA_TCC_XEVT2 17
#define EDMA_TCC_REVT2 18
#define EDMA_TCC_TINT2 19
#define EDMA_TCC_SDINTB 20
#define EDMA_TCC_PCI 21
#define EDMA_TCC_CPU1 22
#define EDMA_TCC_CPU2 23
#define EDMA_TCC_CPU3 24
#define EDMA_TCC_CPU4 25
#define EDMA_TCC_CPU5 26
#define EDMA_TCC_CPU6 27
#define EDMA_TCC_VCPREVT 28
#define EDMA_TCC_VCPXEVT 29
#define EDMA_TCC_TCPREVT 30
#define EDMA_TCC_TCPXEVT 31
#define EDMA_TCC_UREVT 32
#define EDMA_TCC_UXEVT 40
#define EDMA_TCC_GPINT8 48
#define EDMA_TCC_GPINT9 49
#define EDMA_TCC_GPINT10 50
#define EDMA_TCC_GPINT11 51
#define EDMA_TCC_GPINT12 52
#define EDMA_TCC_GPINT13 53
#define EDMA_TCC_GPINT14 54
#define EDMA_TCC_GPINT15 55
#define EDMA_TCC_CHAIN1 56
#define EDMA_TCC_CHAIN2 57
#define EDMA_TCC_CHAIN3 58
#define EDMA_TCC_CHAIN4 59
#define EDMA_TCC_CHAIN5 60
#define EDMA_TCC_CHAIN6 61
#define EDMA_TCC_CHAIN7 62
#define EDMA_TCC_QDMA 63
/* Define EDMA Link Channels */
#define EDMA_CHA_LINK0 64 /* System link channel0 for null */
#define EDMA_CHA_LINK1 65 /* System link channel1 for reserved */
#define EDMA_CHA_LINK2 66 /* System link channel2 */
#define EDMA_CHA_LINK3 67 /* System link channel3 */
#define EDMA_CHA_LINK4 68 /* System link channel4 */
#define EDMA_CHA_LINK5 69 /* System link channel5 */
#define EDMA_CHA_LINK6 70 /* System link channel6 */
#define EDMA_CHA_LINK7 71 /* System link channel7 */
#define EDMA_CHA_LINK8 72 /* System link channel8 */
#define EDMA_CHA_LINK9 73 /* System link channel9 */
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