bbu_dd_edmacsl.h

DSP芯片自检测程序

* PQAR3 - EDMA priority queue allocation register 3
*
* PQA - rw
* PQA[2:0] = "0-7", determine the Q3 queue length available to EDMA requests
*
\******************************************************************************/
#define EDMA_PQAR3_ADDR             0x01A0FFCCu
#define EDMA_PQAR3_PQA_MASK         0x00000007u
#define EDMA_PQAR3_PQA_SHIFT        0x00000000u
#define EDMA_PQAR3_PQA_DEFAULT      0x00000006u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* CIPRL - EDMA channel interrupt pending register, low half
*
* CIP - rw
* CIPx, when TCINT bit in OPT is set to 1 and a specific TCC is provided,
*       the EDMA controller sets the CIPx field
* 
\******************************************************************************/
#define EDMA_CIPRL_ADDR             0x01A0FFE4u
#define EDMA_CIPRL_CIP_MASK         0xFFFFFFFFu
#define EDMA_CIPRL_CIP_SHIFT        0x00000000u
#define EDMA_CIPRL_CIP_DEFAULT      0x00000000u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* CIPRH - EDMA channel interrupt pending register, high half
*
* CIP - rw 
* CIPx, when TCINT bit in OPT is set to 1 and a specific TCC is provided,
*       the EDMA controller sets the CIPx field
* 
\******************************************************************************/
#define EDMA_CIPRH_ADDR             0x01A0FFA4u
#define EDMA_CIPRH_CIP_MASK         0xFFFFFFFFu
#define EDMA_CIPRH_CIP_SHIFT        0x00000000u
#define EDMA_CIPRH_CIP_DEFAULT      0x00000000u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* CIERL - EDMA channel interrupt enable register, low half 
*
* CIE - rw 
* CIEx = "1", enable an interrupt for an EDMA channel
* CIEx = "0", disable an interrupt for an EDMA channel
* 
\******************************************************************************/
#define EDMA_CIERL_ADDR             0x01A0FFE8u
#define EDMA_CIERL_CIE_MASK         0xFFFFFFFFu
#define EDMA_CIERL_CIE_SHIFT        0x00000000u
#define EDMA_CIERL_CIE_DEFAULT      0x00000000u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* CIERH - EDMA channel interrupt enable register, high half 
*
* CIE - rw 
* CIEx = "1", enable an interrupt for an EDMA channel
* CIEx = "0", disable an interrupt for an EDMA channel
* 
\******************************************************************************/
#define EDMA_CIERH_ADDR             0x01A0FFA8u
#define EDMA_CIERH_CIE_MASK         0xFFFFFFFFu
#define EDMA_CIERH_CIE_SHIFT        0x00000000u
#define EDMA_CIERH_CIE_DEFAULT      0x00000000u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* CCERL - EDMA channel chain enable register, low half 
*
* CCE - rw 
* CCEx, when TCINT bit in a channel is set to 1, and CCE[TCC] is set to 1,
*       enable the channel is chained by TCC channel
*
\******************************************************************************/
#define EDMA_CCERL_ADDR             0x01A0FFECu
#define EDMA_CCERL_CCE_MASK         0xFFFFFFFFu
#define EDMA_CCERL_CCE_SHIFT        0x00000000u
#define EDMA_CCERL_CCE_DEFAULT      0x00000000u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* CCERH - EDMA channel chain enable register, high half 
*
* CCE - rw 
* CCEx, when TCINT bit in a channel is set to 1, and CCE[TCC] is set to 1,
*       enable the channel is chained by TCC channel
*
\******************************************************************************/
#define EDMA_CCERH_ADDR             0x01A0FFACu
#define EDMA_CCERH_CCE_MASK         0xFFFFFFFFu
#define EDMA_CCERH_CCE_SHIFT        0x00000000u
#define EDMA_CCERH_CCE_DEFAULT      0x00000000u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* ERL - EDMA event register, low half 
*
* EVT - r
* EVTx = "1", There is event captured by the EDMA
* EVTx = "0", There is no event captured by the EDMA
*  
\******************************************************************************/
#define EDMA_ERL_ADDR               0x01A0FFF0u
#define EDMA_ERL_EVT_MASK           0xFFFFFFFFu
#define EDMA_ERL_EVT_SHIFT          0x00000000u
#define EDMA_ERL_EVT_DEFAULT        0x00000000u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* ERH - EDMA event register, high half 
*
* EVT - r
* EVTx = "1", There is event captured by the EDMA
* EVTx = "0", There is no event captured by the EDMA
*  
\******************************************************************************/
#define EDMA_ERH_ADDR               0x01A0FFB0u
#define EDMA_ERH_EVT_MASK           0xFFFFFFFFu
#define EDMA_ERH_EVT_SHIFT          0x00000000u
#define EDMA_ERH_EVT_DEFAULT        0x00000000u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* EERL - EDMA event enable register, low half
*
* EE - rw
* EE = "1", enable that event triggering off the channel transfer
* EE = "0", disable that event triggering off the channel transfer
* 
\******************************************************************************/
#define EDMA_EERL_ADDR              0x01A0FFF4u
#define EDMA_EERL_EE_MASK           0xFFFFFFFFu
#define EDMA_EERL_EE_SHIFT          0x00000000u
#define EDMA_EERL_EE_DEFAULT        0x00000000u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* EERH - EDMA event enable register, high half
*
* EE - rw
* EE = "1", enable that event triggering off the channel transfer
* EE = "0", disable that event triggering off the channel transfer
*  
\******************************************************************************/
#define EDMA_EERH_ADDR              0x01A0FFB4u
#define EDMA_EERH_EE_MASK           0xFFFFFFFFu
#define EDMA_EERH_EE_SHIFT          0x00000000u
#define EDMA_EERH_EE_DEFAULT        0x00000000u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* EPRL - EDMA event polarity register, low half
*
* EP - rw 
* EPx = "1", select falling edge to determine when an event is triggered
*            on its input
* EPx = "0", select rising edge to determine when an event is triggered
*            on its input
*.
\******************************************************************************/
#define EDMA_EPRL_ADDR              0x01A0FFDCu
#define EDMA_EPRL_EP_MASK           0xFFFFFFFFu
#define EDMA_EPRL_EP_SHIFT          0x00000000u
#define EDMA_EPRL_EP_DEFAULT        0x00000000u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* EPRH - EDMA event polarity register, high half
*
* EP - rw
* EPx = "1", select falling edge to determine when an event is triggered
*            on its input
* EPx = "0", select rising edge to determine when an event is triggered
*            on its input
*. 
\******************************************************************************/
#define EDMA_EPRH_ADDR              0x01A0FF9Cu
#define EDMA_EPRH_EP_MASK           0xFFFFFFFFu
#define EDMA_EPRH_EP_SHIFT          0x00000000u
#define EDMA_EPRH_EP_DEFAULT        0x00000000u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* ECRL - EDMA event clear register, low half
*
* EC - rw
* ECx = "1", clear that event in ER register
*
\******************************************************************************/
#define EDMA_ECRL_ADDR              0x01A0FFF8u
#define EDMA_ECRL_EC_MASK           0xFFFFFFFFu
#define EDMA_ECRL_EC_SHIFT          0x00000000u
#define EDMA_ECRL_EC_DEFAULT        0x00000000u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* ECRH - EDMA event clear register, high half
*
* EC - rw
* ECx = "1", clear that event in ER register
* 
\******************************************************************************/
#define EDMA_ECRH_ADDR              0x01A0FFB8u
#define EDMA_ECRH_EC_MASK           0xFFFFFFFFu
#define EDMA_ECRH_EC_SHIFT          0x00000000u
#define EDMA_ECRH_EC_DEFAULT        0x00000000u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* ESRL - EDMA event set register, low half
*
* ES - rw
* ESx = "1", set that event in ER register
*
\******************************************************************************/
#define EDMA_ESRL_ADDR              0x01A0FFFCu
#define EDMA_ESRL_ES_MASK           0xFFFFFFFFu
#define EDMA_ESRL_ES_SHIFT          0x00000000u
#define EDMA_ESRL_ES_DEFAULT        0x00000000u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* ESRH - EDMA event set register, high half
*
* ES - rw
* ESx = "1", set that event in ER register
* 
\******************************************************************************/
#define EDMA_ESRH_ADDR              0x01A0FFBCu
#define EDMA_ESRH_ES_MASK           0xFFFFFFFFu
#define EDMA_ESRH_ES_SHIFT          0x00000000u
#define EDMA_ESRH_ES_DEFAULT        0x00000000u
/*----------------------------------------------------------------------------*/

/******************************************************************************\
* EDMA Raw Registers Access Macro Definitions
\******************************************************************************/
#define EDMA_RSET(REG,x)            (*(volatile Uint32*)(EDMA_##REG##_ADDR))=((Uint32)(x))
#define EDMA_RGET(REG)              (Uint32)(*(volatile Uint32*)(EDMA_##REG##_ADDR))

#define EDMA_FSET(REG,FIELD,x)      EDMA_RSET(##REG, (EDMA_RGET(##REG) & ~EDMA_##REG##_##FIELD##_MASK) \
                                    | (((Uint32)(x) << EDMA_##REG##_##FIELD##_SHIFT) & EDMA_##REG##_##FIELD##_MASK))

#define EDMA_FGET(REG,FIELD)        (Uint32)((((Uint32)(*(volatile Uint32*)(EDMA_##REG##_ADDR))) \
                                    & EDMA_##REG##_##FIELD##_MASK) >> EDMA_##REG##_##FIELD##_SHIFT) 
/*----------------------------------------------------------------------------*/


/******************************************************************************\
*                 QDMA Registers Macro Definitions
*  
* QOPT    - QDMA options register
*
* PRI[31:29]     - rw, priority levels for QDMA
* ESIZE[28:27]   - rw, element size bits
* 2DS[26]        - rw, source dimension bit
* SUM[25:24]     - rw, source address update mode bits
* 2DD[23]        - rw, destination dimension bit
* DUM[22:21]     - rw, destination address update mode bits
* TCINT[20]      - rw, transfer complete interrupt bit
* TCC[19:16]     - rw, transfer complete code bits
* TCCM[14:13]    - rw, transfer complete code most-significant bits
* FS[0]          - rw, frame synchronization bit
*
\******************************************************************************/
#define QDMA_QOPT_ADDR              0x02000000u
#define QDMA_QOPT_DEFAULT           0x00000000u 

#define QDMA_QOPT_PRI_MASK          0xE0000000u
#define QDMA_QOPT_PRI_SHIFT         0x0000001Du
#define QDMA_QOPT_PRI_DEFAULT       0x00000000u
#define QDMA_QOPT_PRI_URGENT        0x00000000u
#define QDMA_QOPT_PRI_HIGH          0x00000001u
#define QDMA_QOPT_PRI_MEDIUM        0x00000002u
#define QDMA_QOPT_PRI_LOW           0x00000003u

#define QDMA_QOPT_ESIZE_MASK        0x18000000u
#define QDMA_QOPT_ESIZE_SHIFT       0x0000001Bu
#define QDMA_QOPT_ESIZE_DEFAULT     0x00000000u
#define QDMA_QOPT_ESIZE_32BIT       0x00000000u
#define QDMA_QOPT_ESIZE_16BIT       0x00000001u
#define QDMA_QOPT_ESIZE_8BIT        0x10000002u

#define QDMA_QOPT_2DS_MASK          0x04000000u
#define QDMA_QOPT_2DS_SHIFT         0x0000001Au
#define QDMA_QOPT_2DS_DEFAULT       0x00000000u
#define QDMA_QOPT_2DS_NO            0x00000000u
#define QDMA_QOPT_2DS_YES           0x00000001u

#define QDMA_QOPT_SUM_MASK          0x03000000u
#define QDMA_QOPT_SUM_SHIFT         0x00000018u
#define QDMA_QOPT_SUM_DEFAULT       0x00000000u
#define QDMA_QOPT_SUM_NONE          0x00000000u
#define QDMA_QOPT_SUM_INC           0x00000001u
#define QDMA_QOPT_SUM_DEC           0x00000002u
#define QDMA_QOPT_SUM_IDX           0x00000003u

#define QDMA_QOPT_2DD_MASK          0x00800000u
#define QDMA_QOPT_2DD_SHIFT         0x00000017u
#define QDMA_QOPT_2DD_DEFAULT       0x00000000u
#define QDMA_QOPT_2DD_NO            0x00000000u
#define QDMA_QOPT_2DD_YES           0x00000001u

#define QDMA_QOPT_DUM_MASK          0x00600000u
#define QDMA_QOPT_DUM_SHIFT         0x00000015u
#define QDMA_QOPT_DUM_DEFAULT       0x00000000u
#define QDMA_QOPT_DUM_NONE          0x00000000u
#define QDMA_QOPT_DUM_INC           0x00000001u
#define QDMA_QOPT_DUM_DEC           0x00000002u
#define QDMA_QOPT_DUM_IDX           0x00000003u

#define QDMA_QOPT_TCINT_MASK        0x00100000u
#define QDMA_QOPT_TCINT_SHIFT       0x00000014u
#define QDMA_QOPT_TCINT_DEFAULT     0x00000000u
#define QDMA_QOPT_TCINT_NO          0x00000000u
#define QDMA_QOPT_TCINT_YES         0x00000001u

#define QDMA_QOPT_TCC_MASK          0x000F0000u
#define QDMA_QOPT_TCC_SHIFT         0x00000010u
#define QDMA_QOPT_TCC_DEFAULT       0x00000000u
 
#define QDMA_QOPT_TCCM_MASK         0x00006000u
#define QDMA_QOPT_TCCM_SHIFT        0x0000000Du
#define QDMA_QOPT_TCCM_DEFAULT      0x00000000u

#define QDMA_QOPT_FS_MASK           0x00000001u
#define QDMA_QOPT_FS_SHIFT          0x00000000u
#define QDMA_QOPT_FS_DEFAULT        0x00000000u
#define QDMA_QOPT_FS_NO             0x00000000u
#define QDMA_QOPT_FS_YES            0x00000001u

/******************************************************************************\
*                 QDMA Registers Macro Definitions
*  
* QSRC    - QDMA source address register
*
* SRC[31:0]      - rw, specifies the starting byte address of the source
*
\******************************************************************************/
#define QDMA_QSRC_ADDR              0x02000004u
#define QDMA_QSRC_DEFAULT           0x00000000u
 
#define QDMA_QSRC_SRC_MASK          0xFFFFFFFFu