bbu_dd_edmacsl.h

DSP芯片自检测程序

/*******************************************************************************
* COPYRIGHT (C)             中国普天研究院									   *
********************************************************************************
* 源文件名: BBU_DD_EdmaCsl.h                                                   *
* 功能描述：Registers Description for EDMA in TMS320C6414 and TMS320C6416      *
* 编写者：louyajun                                                             *
* 版本：1.0.0                                                                  *
* 编制日期：07/08/2004                                                         *
* 说明：                                                                       *
* 修改历史：                                                                   *
*                                                                              *
*******************************************************************************/

/*------------------------------------------------------------------------------
* Registers and Parameters Description for EDMA in TMS320C6414 and TMS320C6416 
*
* OPT    - EDMA options parameter
* SRC    - EDMA source address parameter
* CNT    - EDMA transfer count parameter
* DST    - EDMA destination address parameter
* IDX    - EDMA index parameter
* RLD    - EDMA count reload + link parameter
*
* PQSR   - EDMA priority queue status register
*
* PQAR0  - EDMA priority queue allocation register 0
* PQAR1  - EDMA priority queue allocation register 1
* PQAR2  - EDMA priority queue allocation register 2
* PQAR3  - EDMA priority queue allocation register 3
*
* CIPRL  - EDMA channel interrupt pending register, low half
* CIPRH  - EDMA channel interrupt pending register, high half
*
* CIERL  - EDMA channel interrupt enable register, low half
* CIERH  - EDMA channel interrupt enable register, high half
*
* CCERL  - EDMA channel chain enable register, low half
* CCERH  - EDMA channel chain enable register, high half
* 
* ERL    - EDMA event register, low half
* ERH    - EDMA event register, high half
* 
* EERL   - EDMA event enable register, low half
* EERH   - EDMA event enable register, high half
*
* EPRL   - EDMA event polarity register, low half
* EPRH   - EDMA event polarity register, high half
* 
* ECRL   - EDMA event clear register, low half
* ECRH   - EDMA event clear register, high half
* 
* ESRL   - EDMA event set register, low half
* ESRH   - EDMA event set register, high half
* 
* QOPT   - QDMA options register
* QSRC   - QDMA source address register
* QCNT   - QDMA transfer count register
* QDST   - QDMA destination address register
* QIDX   - QDMA index register

* QSOPT  - QDMA options pseudo register
* QSSRC  - QDMA source address pseudo register
* QSCNT  - QDMA transfer count pseudo register
* QSDST  - QDMA destination address pseudo register
* QSIDX  - QDMA index pseudo register
*
\******************************************************************************/

#ifndef _BBU_DD_EDMACSL_H_
#define _BBU_DD_EDMACSL_H_

#include "BBU_DD_Stdinc.h"
#include "BBU_DD_IrqCsl.h"

/******************************************************************************\
*                 EDMA Parameter Macro Definitions
*  
* OPT    - EDMA options parameter
*
* PRI[31:29]     - rw, priority levels for EDMA events bits
* ESIZE[28:27]   - rw, element size bits
* 2DS[26]        - rw, source dimension bit
* SUM[25:24]     - rw, source address update mode bits
* 2DD[23]        - rw, destination dimension bit
* DUM[22:21]     - rw, destination address update mode bits
* TCINT[20]      - rw, transfer complete interrupt bit
* TCC[19:16]     - rw, transfer complete code bits
* TCCM[14:13]    - rw, transfer complete code most-significant bits
* ATCINT[12]     - rw, alternate transfer complete interrupt bit
* ATCC[10:5]     - rw, alternate transfer complete code bits
* PDTS[3]        - rw, peripheral device transfer mode for source bit
* PDTD[2]        - rw, peripheral device transfer mode for destination bit
* LINK[1]        - rw, linking of event parameters enable bit
* FS[0]          - rw, frame synchronization bit
*
\******************************************************************************/
#define EDMA_OPT_OFFSET             0
#define EDMA_OPT_DEFAULT            0x00000000u 

#define EDMA_OPT_PRI_MASK           0xE0000000u
#define EDMA_OPT_PRI_SHIFT          0x0000001Du
#define EDMA_OPT_PRI_DEFAULT        0x00000000u
#define EDMA_OPT_PRI_URGENT         0x00000000u
#define EDMA_OPT_PRI_HIGH           0x00000001u
#define EDMA_OPT_PRI_MEDIUM         0x00000002u
#define EDMA_OPT_PRI_LOW            0x00000003u

#define EDMA_OPT_ESIZE_MASK         0x18000000u
#define EDMA_OPT_ESIZE_SHIFT        0x0000001Bu
#define EDMA_OPT_ESIZE_DEFAULT      0x00000000u
#define EDMA_OPT_ESIZE_32BIT        0x00000000u
#define EDMA_OPT_ESIZE_16BIT        0x00000001u
#define EDMA_OPT_ESIZE_8BIT         0x10000002u

#define EDMA_OPT_2DS_MASK           0x04000000u
#define EDMA_OPT_2DS_SHIFT          0x0000001Au
#define EDMA_OPT_2DS_DEFAULT        0x00000000u
#define EDMA_OPT_2DS_NO             0x00000000u
#define EDMA_OPT_2DS_YES            0x00000001u

#define EDMA_OPT_SUM_MASK           0x03000000u
#define EDMA_OPT_SUM_SHIFT          0x00000018u
#define EDMA_OPT_SUM_DEFAULT        0x00000000u
#define EDMA_OPT_SUM_NONE           0x00000000u
#define EDMA_OPT_SUM_INC            0x00000001u
#define EDMA_OPT_SUM_DEC            0x00000002u
#define EDMA_OPT_SUM_IDX            0x00000003u

#define EDMA_OPT_2DD_MASK           0x00800000u
#define EDMA_OPT_2DD_SHIFT          0x00000017u
#define EDMA_OPT_2DD_DEFAULT        0x00000000u
#define EDMA_OPT_2DD_NO             0x00000000u
#define EDMA_OPT_2DD_YES            0x00000001u

#define EDMA_OPT_DUM_MASK           0x00600000u
#define EDMA_OPT_DUM_SHIFT          0x00000015u
#define EDMA_OPT_DUM_DEFAULT        0x00000000u
#define EDMA_OPT_DUM_NONE           0x00000000u
#define EDMA_OPT_DUM_INC            0x00000001u
#define EDMA_OPT_DUM_DEC            0x00000002u
#define EDMA_OPT_DUM_IDX            0x00000003u

#define EDMA_OPT_TCINT_MASK         0x00100000u
#define EDMA_OPT_TCINT_SHIFT        0x00000014u
#define EDMA_OPT_TCINT_DEFAULT      0x00000000u
#define EDMA_OPT_TCINT_NO           0x00000000u
#define EDMA_OPT_TCINT_YES          0x00000001u

#define EDMA_OPT_TCC_MASK           0x000F0000u
#define EDMA_OPT_TCC_SHIFT          0x00000010u
#define EDMA_OPT_TCC_DEFAULT        0x00000000u
 
#define EDMA_OPT_TCCM_MASK          0x00006000u
#define EDMA_OPT_TCCM_SHIFT         0x0000000Du
#define EDMA_OPT_TCCM_DEFAULT       0x00000000u

#define EDMA_OPT_ATCINT_MASK        0x00001000u
#define EDMA_OPT_ATCINT_SHIFT       0x0000000Cu
#define EDMA_OPT_ATCINT_DEFAULT     0x00000000u
#define EDMA_OPT_ATCINT_NO          0x00000000u
#define EDMA_OPT_ATCINT_YES         0x00000001u

#define EDMA_OPT_ATCC_MASK          0x000007E0u
#define EDMA_OPT_ATCC_SHIFT         0x00000005u
#define EDMA_OPT_ATCC_DEFAULT       0x00000000u

#define EDMA_OPT_PDTS_MASK          0x00000008u
#define EDMA_OPT_PDTS_SHIFT         0x00000003u
#define EDMA_OPT_PDTS_DEFAULT       0x00000000u
#define EDMA_OPT_PDTS_DISABLE       0x00000000u
#define EDMA_OPT_PDTS_ENABLE        0x00000001u

#define EDMA_OPT_PDTD_MASK          0x00000004u
#define EDMA_OPT_PDTD_SHIFT         0x00000002u
#define EDMA_OPT_PDTD_DEFAULT       0x00000000u
#define EDMA_OPT_PDTD_DISABLE       0x00000000u
#define EDMA_OPT_PDTD_ENABLE        0x00000001u

#define EDMA_OPT_LINK_MASK          0x00000002u
#define EDMA_OPT_LINK_SHIFT         0x00000001u
#define EDMA_OPT_LINK_DEFAULT       0x00000000u
#define EDMA_OPT_LINK_NO            0x00000000u
#define EDMA_OPT_LINK_YES           0x00000001u

#define EDMA_OPT_FS_MASK            0x00000001u
#define EDMA_OPT_FS_SHIFT           0x00000000u
#define EDMA_OPT_FS_DEFAULT         0x00000000u
#define EDMA_OPT_FS_NO              0x00000000u
#define EDMA_OPT_FS_YES             0x00000001u

/******************************************************************************\
*                 EDMA Parameter Macro Definitions
*  
* SRC    - EDMA source address parameter
*
* SRC[31:0]      - rw, specifies the starting byte address of the source
*
\******************************************************************************/
#define EDMA_SRC_OFFSET             1
#define EDMA_SRC_DEFAULT            0x00000000u
 
#define EDMA_SRC_SRC_MASK           0xFFFFFFFFu
#define EDMA_SRC_SRC_SHIFT          0x00000000u
#define EDMA_SRC_SRC_DEFAULT        0x00000000u

/******************************************************************************\
*                 EDMA Parameter Macro Definitions
*  
* CNT    - EDMA transfer count parameter
*
* FRMCNT[31:16]  - rw, FRMCNT + 1 specifies the number of frames in a 1D block
*                      or number of arrays in a 2D block
* ELECNT[15:0]   - rw, ELECNT specifies the number of elements in a frame
*                      or an array.
*
\******************************************************************************/
#define EDMA_CNT_OFFSET             2
#define EDMA_CNT_DEFAULT            0x00000000u

#define EDMA_CNT_FRMCNT_MASK        0xFFFF0000u
#define EDMA_CNT_FRMCNT_SHIFT       0x00000010u
#define EDMA_CNT_FRMCNT_DEFAULT     0x00000000u

#define EDMA_CNT_ELECNT_MASK        0x0000FFFFu
#define EDMA_CNT_ELECNT_SHIFT       0x00000000u
#define EDMA_CNT_ELECNT_DEFAULT     0x00000000u

/******************************************************************************\
*                 EDMA Parameter Macro Definitions
*  
* DST    - EDMA destination address parameter
*
* DST[31:0]      - rw,specifies the starting byte address of the destination
*
\******************************************************************************/
#define EDMA_DST_OFFSET             3
#define EDMA_DST_DEFAULT            0x00000000u

#define EDMA_DST_DST_MASK           0xFFFFFFFFu
#define EDMA_DST_DST_SHIFT          0x00000000u
#define EDMA_DST_DST_DEFAULT        0x00000000u

/******************************************************************************\
*                 EDMA Parameter Macro Definitions
*  
* IDX    - EDMA index parameter
*
* FRMIDX[31:16]  - rw, frame or array index bits
* ELEIDX[15:0]   - rw, element index bits
*
\******************************************************************************/
#define EDMA_IDX_OFFSET             4
#define EDMA_IDX_DEFAULT            0x00000000u
 
#define EDMA_IDX_FRMIDX_MASK        0xFFFF0000u
#define EDMA_IDX_FRMIDX_SHIFT       0x00000010u
#define EDMA_IDX_FRMIDX_DEFAULT     0x00000000u

#define EDMA_IDX_ELEIDX_MASK        0x0000FFFFu
#define EDMA_IDX_ELEIDX_SHIFT       0x00000000u
#define EDMA_IDX_ELEIDX_DEFAULT     0x00000000u

/******************************************************************************\
*                 EDMA Parameter Macro Definitions
*  
* RLD - EDMA count reload/link parameter
*
* ELERLD[31:16]  - rw, element count reload bits
* LINK[15:0]     - rw, specifies the lower 16-bit address in the parameter RAM
*                      from which the EDMA loads/reloads the parameters of the
*                      next event in the chain
*
\******************************************************************************/
#define EDMA_RLD_OFFSET             5
#define EDMA_RLD_DEFAULT            0x00000000u

#define EDMA_RLD_ELERLD_MASK        0xFFFF0000u
#define EDMA_RLD_ELERLD_SHIFT       0x00000010u
#define EDMA_RLD_ELERLD_DEFAULT     0x00000000u

#define EDMA_RLD_LINK_MASK          0x0000FFFFu
#define EDMA_RLD_LINK_SHIFT         0x00000000u
#define EDMA_RLD_LINK_DEFAULT       0x00000000u

/******************************************************************************\
* Handle Based EDMA Parameter Macro Definitions
\******************************************************************************/
#define EDMA_ADDRH(h,REG)           ((((Uint32)(h)) & 0x0000FFFF) + EDMA_PRAM_START \
                                    + (EDMA_##REG##_OFFSET<<2))

#define EDMA_RSETH(h,REG,x)         (*(volatile Uint32*)(EDMA_ADDRH(h,##REG)))=((Uint32)(x))
#define EDMA_RGETH(h,REG)           (*(volatile Uint32*)(EDMA_ADDRH(h,##REG)))

#define EDMA_FSETH(h,REG,FIELD,x)   EDMA_RSETH(h,##REG, (EDMA_RGETH(h,##REG) & ~EDMA_##REG##_##FIELD##_MASK) \
                                    | (((Uint32)(x) << EDMA_##REG##_##FIELD##_SHIFT) & EDMA_##REG##_##FIELD##_MASK))

#define EDMA_FGETH(h,REG,FIELD)     (Uint32)((((Uint32)(*(volatile Uint32*)(EDMA_ADDRH(h,##REG)))) \
                                    & EDMA_##REG##_##FIELD##_MASK) >> EDMA_##REG##_##FIELD##_SHIFT) 
/*----------------------------------------------------------------------------*/


/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* PQSR - EDMA priority queue status register
*
* PQ - r
* PQx = "1", there are no requests pending in the respective priority level queue
* PQx = "0", there are requests pending in the respective priority level queue
*
\******************************************************************************/
#define EDMA_PQSR_ADDR              0x01A0FFE0u
#define EDMA_PQSR_PQ_MASK           0x0000000Fu
#define EDMA_PQSR_PQ_SHIFT          0x00000000u
#define EDMA_PQSR_PQ_DEFAULT        0x0000000Fu

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* PQAR0 - EDMA priority queue allocation register 0
*
* PQA - rw
* PQA[2:0] = "0-7", determine the Q0 queue length available to EDMA requests
*
\******************************************************************************/
#define EDMA_PQAR0_ADDR             0x01A0FFC0u
#define EDMA_PQAR0_PQA_MASK         0x00000007u
#define EDMA_PQAR0_PQA_SHIFT        0x00000000u
#define EDMA_PQAR0_PQA_DEFAULT      0x00000002u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* PQAR1 - EDMA priority queue allocation register 1
*
* PQA - rw
* PQA[2:0] = "0-7", determine the Q1 queue length available to EDMA requests
*
\******************************************************************************/
#define EDMA_PQAR1_ADDR             0x01A0FFC4u
#define EDMA_PQAR1_PQA_MASK         0x00000007u
#define EDMA_PQAR1_PQA_SHIFT        0x00000000u
#define EDMA_PQAR1_PQA_DEFAULT      0x00000006u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
* 
* PQAR2 - EDMA priority queue allocation register 2
*  
* PQA - rw
* PQA[2:0] = "0-7", determine the Q2 queue length available to EDMA requests
*
\******************************************************************************/
#define EDMA_PQAR2_ADDR             0x01A0FFC8u
#define EDMA_PQAR2_PQA_MASK         0x00000007u
#define EDMA_PQAR2_PQA_SHIFT        0x00000000u
#define EDMA_PQAR2_PQA_DEFAULT      0x00000002u

/******************************************************************************\
*                 EDMA Registers Macro Definitions
*