module_testbench.v

来自「AES算法的verilog代码」· Verilog 代码 · 共 25 行

module TB(); // ????
reg            clk;
reg  [127:0]   in1;
reg  [127:0]   in2;
wire [127:0]   out1;
wire [127:0]   out2;
always #5 clk=~clk;
initial
begin
    clk=0;
    #10  in1=128'h00112233445566778899aabbccddeeff;
         in2=128'h000102030405060708090a0b0c0d0e0f; 
    #1200 $finish; 
end
    initial
    $monitor($time,"all_rout=%h",out1);
all   U_all(
         .all_rin(in1),
         .all_kin(in2),
         .all_rout(out1),
         .all_kout(out2),
         .clk(clk)
          );
endmodule