countroller.rpt
来自「主次干道分别亮59s和11s」· RPT 代码 · 共 838 行 · 第 1/3 页
RPT
838 行
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - -- INPUT G ^ 0 0 0 0 Clock
183 - - - -- INPUT ^ 0 0 0 7 CountNum0
8 - - A -- INPUT ^ 0 0 0 5 CountNum1
7 - - A -- INPUT ^ 0 0 0 3 CountNum2
9 - - A -- INPUT ^ 0 0 0 3 CountNum3
78 - - - -- INPUT ^ 0 0 0 6 CountNum4
80 - - - -- INPUT ^ 0 0 0 6 CountNum5
184 - - - -- INPUT ^ 0 0 0 13 CountNum6
182 - - - -- INPUT ^ 0 0 0 9 Hold
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\kkk\countroller.rpt
countroller
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
102 - - - 03 OUTPUT 0 1 0 0 GreenA
103 - - - 02 OUTPUT 0 1 0 0 GreenB
162 - - - 05 OUTPUT 0 1 0 0 NumA0
104 - - - 01 OUTPUT 0 1 0 0 NumA1
157 - - - 01 OUTPUT 0 1 0 0 NumA2
158 - - - 02 OUTPUT 0 1 0 0 NumA3
161 - - - 04 OUTPUT 0 1 0 0 NumA4
159 - - - 03 OUTPUT 0 1 0 0 NumA5
148 - - A -- OUTPUT 0 1 0 0 NumB0
147 - - A -- OUTPUT 0 1 0 0 NumB1
149 - - A -- OUTPUT 0 1 0 0 NumB2
150 - - A -- OUTPUT 0 1 0 0 NumB3
10 - - A -- OUTPUT 0 1 0 0 NumB4
11 - - A -- OUTPUT 0 1 0 0 NumB5
167 - - - 08 OUTPUT 0 1 0 0 RedA
169 - - - 10 OUTPUT 0 1 0 0 RedB
160 - - - 04 OUTPUT 0 1 0 0 YellowA
170 - - - 11 OUTPUT 0 1 0 0 YellowB
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\kkk\countroller.rpt
countroller
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 02 AND2 ! 1 1 0 4 |LPM_ADD_SUB:261|addcore:adder|pcarry3
- 4 - A 03 AND2 ! 1 1 0 3 |LPM_ADD_SUB:261|addcore:adder|pcarry4
- 7 - A 02 OR2 ! 3 0 0 3 |LPM_ADD_SUB:261|addcore:adder|:125
- 3 - A 04 DFFE + 1 1 1 0 :10
- 2 - A 04 DFFE + 1 1 1 0 :12
- 4 - A 02 DFFE + 1 1 1 0 :14
- 1 - A 01 DFFE + 1 1 1 0 :16
- 3 - A 02 DFFE + 1 1 1 0 :18
- 1 - A 05 DFFE + 2 1 1 0 :20
- 7 - A 07 DFFE + 3 0 1 0 :22
- 5 - A 09 DFFE + 2 0 1 0 :24
- 1 - A 02 DFFE + 2 2 1 0 :26
- 3 - A 01 DFFE + 3 1 1 0 :28
- 8 - A 01 DFFE + 2 1 1 0 :30
- 5 - A 06 DFFE + 2 1 1 0 :32
- 1 - A 08 DFFE + 2 0 1 0 :34
- 2 - A 03 DFFE + 3 1 1 0 :36
- 3 - A 03 DFFE + 3 1 1 0 :38
- 1 - A 10 DFFE + 1 0 1 0 :40
- 2 - A 01 DFFE + 0 1 1 0 :42
- 1 - A 11 DFFE + 1 1 1 0 :44
- 1 - A 03 OR2 2 1 0 5 :148
- 4 - A 04 OR2 3 1 0 1 :407
- 1 - A 04 OR2 2 2 0 1 :422
- 5 - A 02 OR2 1 2 0 1 :434
- 4 - A 01 OR2 3 1 0 1 :446
- 6 - A 02 OR2 2 1 0 1 :458
- 1 - A 12 OR2 2 1 0 4 :600
- 5 - A 01 AND2 1 1 0 3 :867
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\kkk\countroller.rpt
countroller
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/144( 3%) 7/ 72( 9%) 0/ 72( 0%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\kkk\countroller.rpt
countroller
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 18 Clock
Device-Specific Information: f:\kkk\countroller.rpt
countroller
** EQUATIONS **
Clock : INPUT;
CountNum0 : INPUT;
CountNum1 : INPUT;
CountNum2 : INPUT;
CountNum3 : INPUT;
CountNum4 : INPUT;
CountNum5 : INPUT;
CountNum6 : INPUT;
Hold : INPUT;
-- Node name is 'GreenA'
-- Equation name is 'GreenA', type is output
GreenA = _LC2_A3;
-- Node name is 'GreenB'
-- Equation name is 'GreenB', type is output
GreenB = _LC2_A1;
-- Node name is 'NumA0'
-- Equation name is 'NumA0', type is output
NumA0 = _LC1_A5;
-- Node name is 'NumA1'
-- Equation name is 'NumA1', type is output
NumA1 = _LC3_A2;
-- Node name is 'NumA2'
-- Equation name is 'NumA2', type is output
NumA2 = _LC1_A1;
-- Node name is 'NumA3'
-- Equation name is 'NumA3', type is output
NumA3 = _LC4_A2;
-- Node name is 'NumA4'
-- Equation name is 'NumA4', type is output
NumA4 = _LC2_A4;
-- Node name is 'NumA5'
-- Equation name is 'NumA5', type is output
NumA5 = _LC3_A4;
-- Node name is 'NumB0'
-- Equation name is 'NumB0', type is output
NumB0 = _LC5_A6;
-- Node name is 'NumB1'
-- Equation name is 'NumB1', type is output
NumB1 = _LC8_A1;
-- Node name is 'NumB2'
-- Equation name is 'NumB2', type is output
NumB2 = _LC3_A1;
-- Node name is 'NumB3'
-- Equation name is 'NumB3', type is output
NumB3 = _LC1_A2;
-- Node name is 'NumB4'
-- Equation name is 'NumB4', type is output
NumB4 = _LC5_A9;
-- Node name is 'NumB5'
-- Equation name is 'NumB5', type is output
NumB5 = _LC7_A7;
-- Node name is 'RedA'
-- Equation name is 'RedA', type is output
RedA = _LC1_A8;
-- Node name is 'RedB'
-- Equation name is 'RedB', type is output
RedB = _LC1_A10;
-- Node name is 'YellowA'
-- Equation name is 'YellowA', type is output
YellowA = _LC3_A3;
-- Node name is 'YellowB'
-- Equation name is 'YellowB', type is output
YellowB = _LC1_A11;
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